commit e99f7a9bb0e1fe65bb38f0061b2e2c6fb81b7299
parent c69525f5851255dade7ffad05837cc5041d90792
Author: Matsuda Kenji <info@mtkn.jp>
Date: Mon, 3 Apr 2023 12:20:26 +0900
update
Diffstat:
2 files changed, 7 insertions(+), 91 deletions(-)
diff --git a/boot2/boot2.S b/boot2/boot2.S
@@ -35,7 +35,7 @@ boot2:
// set 1-cycle sample delay.
mov r1, #1
- mov r2, #0xf0
+ mov r2, #0xa0
str r1, [r0, r2] // SSI: RX_SAMPLE_DLY
// setup sregs
@@ -60,13 +60,13 @@ boot2:
// set sreg
mov r1, #0x31 // write status register-2
str r1, [r0, #0x60] // SSI: DR0
- //mov r1, #0 // is this needed?
- //str r1, [r0, #0x60] // SSI: DR0 is this needed?
+ mov r1, #0 // is this needed?
+ str r1, [r0, #0x60] // SSI: DR0 is this needed?
mov r1, #0x2 // quad enable
str r1, [r0, #0x60] // SSI: DR0
bl wait_ssi
ldr r1, [r0, #0x60] // SSI: DR0
- //ldr r1, [r0, #0x60] // SSI: DR0
+ ldr r1, [r0, #0x60] // SSI: DR0
ldr r1, [r0, #0x60] // SSI: DR0
wait_sreg_lock:
@@ -114,7 +114,7 @@ wait_sreg_lock:
mov r1, #0xeb // fast read quad i/o
str r1, [r0, #0x60] // SSI: DR0
- mov r1, #0xf0 // 0xa0 is for w25q80bv. 0xf0 is for w25q16j
+ mov r1, #0xa0 // 0xa0 is for w25q80bv. 0xf0 is for w25q16j??
str r1, [r0, #0x60] // SSI: DR0
bl wait_ssi
// I think I need to read rxd-fifo
@@ -123,7 +123,7 @@ wait_sreg_lock:
mov r1, #0
str r1, [r0, #0x8] // SSI: SSIENR
- mov r1, #0xf0
+ mov r1, #0xa0
lsl r1, r1, #24
mov r2, #4 // 4 dummy clocks
lsl r2, r2, #11 // WAIT_CYCLES
diff --git a/boot2/boot2_w25q.S b/boot2/boot2_w25q.S
@@ -1,112 +1,28 @@
-// ----------------------------------------------------------------------------
-// Second stage boot code
-// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
-// SPDX-License-Identifier: BSD-3-Clause
-//
-// Device: Winbond W25Q080
-// Also supports W25Q16JV (which has some different SR instructions)
-// Also supports AT25SF081
-// Also supports S25FL132K0
-//
-// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode
-//
-// Details: * Check status register 2 to determine if QSPI mode is enabled,
-// and perform an SR2 programming cycle if necessary.
-// * Use SSI to perform a dummy 0xEB read command, with the mode
-// continuation bits set, so that the flash will not require
-// 0xEB instruction prefix on subsequent reads.
-// * Configure SSI to write address, mode bits, but no instruction.
-// SSI + flash are now jointly in a state where continuous reads
-// can take place.
-// * Jump to exit pointer passed in via lr. Bootrom passes null,
-// in which case this code uses a default 256 byte flash offset
-//
-// Building: * This code must be position-independent, and use stack only
-// * The code will be padded to a size of 256 bytes, including a
-// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
-// ----------------------------------------------------------------------------
-
-#include "pico/asm_helper.S"
-#include "hardware/regs/addressmap.h"
-#include "hardware/regs/ssi.h"
-#include "hardware/regs/pads_qspi.h"
-
-// ----------------------------------------------------------------------------
-// Config section
-// ----------------------------------------------------------------------------
-// It should be possible to support most flash devices by modifying this section
-
-// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
-// This must be a positive, even integer.
-// The bootrom is very conservative with SPI frequency, but here we should be
-// as aggressive as possible.
-
-#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 4
-#endif
-#if PICO_FLASH_SPI_CLKDIV & 1
-#error PICO_FLASH_SPI_CLKDIV must be even
-#endif
-
-// Define interface width: single/dual/quad IO
-#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
-
-// For W25Q080 this is the "Read data fast quad IO" instruction:
+#define FRAME_FORMAT 0x2
#define CMD_READ 0xeb
-
-// "Mode bits" are 8 special bits sent immediately after
-// the address bits in a "Read Data Fast Quad I/O" command sequence.
-// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
-// next read does not require the 0xeb instruction prefix.
#define MODE_CONTINUOUS_READ 0xa0
-
-// The number of address + mode bits, divided by 4 (always 4, not function of
-// interface width).
#define ADDR_L 8
-
-// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
-// are required.
#define WAIT_CYCLES 4
-// If defined, we will read status reg, compare to SREG_DATA, and overwrite
-// with our value if the SR doesn't match.
-// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
-// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
-// This isn't great because it will remove block protections.
-// A better solution is to use a volatile SR write if your device supports it.
-#define PROGRAM_STATUS_REG
-
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_STATUS 0x05
#define CMD_READ_STATUS2 0x35
#define CMD_WRITE_STATUS 0x01
#define SREG_DATA 0x02 // Enable quad-SPI mode
-// ----------------------------------------------------------------------------
-// Start of 2nd Stage Boot Code
-// ----------------------------------------------------------------------------
-
.syntax unified
.cpu cortex-m0plus
.thumb
.section .text
-// The exit point is passed in lr. If entered from bootrom, this will be the
-// flash address immediately following this second stage (0x10000100).
-// Otherwise it will be a return address -- second stage being called as a
-// function by user code, after copying out of XIP region. r3 holds SSI base,
-// r0...2 used as temporaries. Other GPRs not used.
.global _stage2_boot
.type _stage2_boot,%function
.thumb_func
_stage2_boot:
push {lr}
- // Set pad configuration:
- // - SCLK 8mA drive, no slew limiting
- // - SDx disable input Schmitt to reduce delay
-
ldr r3, =PADS_QSPI_BASE
movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
