rp2040

commit c69525f5851255dade7ffad05837cc5041d90792
parent 6c3127544f79cb9c7a83fafb6620b32306c460ea
Author: Matsuda Kenji <info@mtkn.jp>
Date:   Mon,  3 Apr 2023 11:50:09 +0900

add generic boot2

Diffstat:
A
boot2/boot2.S.gen
 | 
66
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
A
boot2/boot2_generic.S
 | 
66
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

2 files changed, 132 insertions(+), 0 deletions(-)
diff --git a/boot2/boot2.S.gen b/boot2/boot2.S.gen
@@ -0,0 +1,66 @@
+.cpu cortex-m0
+.thumb
+
+.equ XIP_BASE,     0x10000000
+.equ XIP_SSI_BASE, 0x18000000
+.equ PPB_BASE,     0xe0000000
+
+.section .text
+
+.global _stage2_boot
+.type _stage2_boot,%function
+.thumb_func
+_stage2_boot:
+	push {lr}
+
+	ldr r3, =XIP_SSI_BASE
+
+	mov r1, #0
+	str r1, [r3, #0x8] // SSI_SSIENR
+
+	mov r1, #0x4
+	str r1, [r3, #0x14] // SSI_BAUDR
+
+	mov r1, #0x0
+	lsl r1, r1, #21 // SPI_FRF
+	mov r2, #31
+	lsl r2, r2, #16 // DFS_32
+	add r1, r1, r2
+	mov r2, #0x0
+	lsl r2, r2, #8 // TMOD
+	add r1, r1, r2
+	str r1, [r3, #0x0] // SSI_CTRLR0
+
+	mov r1, #0x03 // read command
+	lsl r1, r1, #24
+	mov r2, #2 // 8bit instruction
+	lsl r2, r2, #8
+	add r1, r1, r2
+	mov r2, #6 // 24bit address length
+	lsl r2, r2, #2
+	add r1, r1, r2
+	ldr r0, =0xf4
+	add r0, r0, r3 // SSI_SPI_CTRLR0
+	str r1, [r0, #0x0]
+
+	mov r1, #0x0
+	str r1, [r3, #0x4] // SSI_CTRLR1_OFFSET
+
+	mov r1, #1
+	str r1, [r3, #0x8] // SSI_SSIENR_OFFSET
+
+	pop {r0}
+	cmp r0, #0
+	beq vector_into_flash
+	bx r0
+vector_into_flash:
+	ldr r0, =XIP_BASE
+	ldr r2, =0x100
+	add r0, r0, r2
+	ldr r1, =PPB_BASE
+	ldr r2, =0xed08 // M0PLUS_VTOR
+	add r1, r1, r2
+	str r0, [r1, #0x0]
+	ldmia r0, {r0, r1}
+	msr msp, r0
+	bx r1
diff --git a/boot2/boot2_generic.S b/boot2/boot2_generic.S
@@ -0,0 +1,66 @@
+.cpu cortex-m0
+.thumb
+
+.equ XIP_BASE,     0x10000000
+.equ XIP_SSI_BASE, 0x18000000
+.equ PPB_BASE,     0xe0000000
+
+.section .text
+
+.global _stage2_boot
+.type _stage2_boot,%function
+.thumb_func
+_stage2_boot:
+	push {lr}
+
+	ldr r3, =XIP_SSI_BASE
+
+	mov r1, #0
+	str r1, [r3, #0x8] // SSI_SSIENR
+
+	mov r1, #0x4
+	str r1, [r3, #0x14] // SSI_BAUDR
+
+	mov r1, #0x0
+	lsl r1, r1, #21 // SPI_FRF
+	mov r2, #31
+	lsl r2, r2, #16 // DFS_32
+	add r1, r1, r2
+	mov r2, #0x0
+	lsl r2, r2, #8 // TMOD
+	add r1, r1, r2
+	str r1, [r3, #0x0] // SSI_CTRLR0
+
+	mov r1, #0x03 // read command
+	lsl r1, r1, #24
+	mov r2, #2 // 8bit instruction
+	lsl r2, r2, #8
+	add r1, r1, r2
+	mov r2, #6 // 24bit address length
+	lsl r2, r2, #2
+	add r1, r1, r2
+	ldr r0, =0xf4
+	add r0, r0, r3 // SSI_SPI_CTRLR0
+	str r1, [r0, #0x0]
+
+	mov r1, #0x0
+	str r1, [r3, #0x4] // SSI_CTRLR1_OFFSET
+
+	mov r1, #1
+	str r1, [r3, #0x8] // SSI_SSIENR_OFFSET
+
+	pop {r0}
+	cmp r0, #0
+	beq vector_into_flash
+	bx r0
+vector_into_flash:
+	ldr r0, =XIP_BASE
+	ldr r2, =0x100
+	add r0, r0, r2
+	ldr r1, =PPB_BASE
+	ldr r2, =0xed08 // M0PLUS_VTOR
+	add r1, r1, r2
+	str r0, [r1, #0x0]
+	ldmia r0, {r0, r1}
+	msr msp, r0
+	bx r1