commit 6c3127544f79cb9c7a83fafb6620b32306c460ea
parent 0918201676de0b392e5bbdbe1dbb355e7edf3a1c
Author: Matsuda Kenji <info@mtkn.jp>
Date: Mon, 3 Apr 2023 11:49:41 +0900
trying to write boot2
Diffstat:
4 files changed, 149 insertions(+), 35 deletions(-)
diff --git a/Makefile b/Makefile
@@ -18,7 +18,7 @@ clean:
rm -f *.uf2
rm -f bincrc
rm -f boot2/*.o
-# rm -f boot2/*.bin
+ rm -f boot2/*.bin
rm -f boot2/boot2_crc.S
start.o: start.s
diff --git a/boot2/boot2.S b/boot2/boot2.S
@@ -1,53 +1,147 @@
-.cpu cortex-m0
+.cpu cortex-m0plus
.thumb
-.equ XIP_BASE, 0x10000000
-.equ XIP_SSI_BASE, 0x18000000
-.equ PPB_BASE, 0xe0000000
+.equ XIP_BASE, 0x10000000
+.equ XIP_SSI_BASE, 0x18000000
+.equ PADS_QSPI_BASE, 0x40020000
+.equ PPB_BASE, 0xe0000000
-.section .text
-
-.global _stage2_boot
-.type _stage2_boot,%function
-.thumb_func
-_stage2_boot:
+boot2:
push {lr}
- ldr r3, =XIP_SSI_BASE
+ ldr r0, =PADS_QSPI_BASE
+ mov r1, #2 // 8mA
+ lsr r1, r1, #4 // SCLK_DRIVE
+ add r1, r1, #1 // slew fast
+ str r1, [r0, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
+ // clear schmitt bit
+ ldr r1, [r0, #0x8] // PADS_QSPI: GPIO_QSPI_SD0
+ mov r2, #0x2 // schmitt trigger
+ bic r1, r2
+ str r1, [r3, #0x8] // PADS_QSPI: GPIO_QSPI_SD0
+ str r1, [r3, #0xc] // PADS_QSPI: GPIO_QSPI_SD1
+ str r1, [r3, #0x10] // PADS_QSPI: GPIO_QSPI_SD2
+ str r1, [r3, #0x14] // PADS_QSPI: GPIO_QSPI_SD3
+
+ ldr r0, =XIP_SSI_BASE
+ // disable ssi
mov r1, #0
- str r1, [r3, #0x8] // SSI_SSIENR
+ str r1, [r0, #0x8] // SSI: SSIENR
+ //set divider
mov r1, #0x4
- str r1, [r3, #0x14] // SSI_BAUDR
+ str r1, [r0, #0x14] // SSI: BAUDR
+
+ // set 1-cycle sample delay.
+ mov r1, #1
+ mov r2, #0xf0
+ str r1, [r0, r2] // SSI: RX_SAMPLE_DLY
+
+ // setup sregs
+ mov r1, #0x7 // 8bit data frame size
+ lsl r1, r1, #16 // DFS_32
+ mov r2, #0 // transmit and recieve
+ lsl r2, r2, #8 // TMOD
+ add r1, r1, r2
+ str r1, [r0, #0] // SSI: CTRLR0
+
+ // enable ssi
+ mov r1, #1
+ str r1, [r0, #0x8] // SSI: SSIENR
+
+ // write enable
+ mov r1, #0x06 // write enable
+ str r1, [r0, #0x60] // SSI: DR0
+ bl wait_ssi
+ ldr r0, =XIP_SSI_BASE
+ ldr r1, [r0, #0x60] // SSI: DR0
+
+ // set sreg
+ mov r1, #0x31 // write status register-2
+ str r1, [r0, #0x60] // SSI: DR0
+ //mov r1, #0 // is this needed?
+ //str r1, [r0, #0x60] // SSI: DR0 is this needed?
+ mov r1, #0x2 // quad enable
+ str r1, [r0, #0x60] // SSI: DR0
+ bl wait_ssi
+ ldr r1, [r0, #0x60] // SSI: DR0
+ //ldr r1, [r0, #0x60] // SSI: DR0
+ ldr r1, [r0, #0x60] // SSI: DR0
+
+wait_sreg_lock:
+ mov r0, #0x35 // read status register-2
+ bl read_sreg
+ mov r1, #1
+ tst r0, r1
+ bne wait_sreg_lock
+
+ // disable ssi again
+ ldr r0, =XIP_SSI_BASE
+ mov r1, #0
+ str r1, [r0, #0x8] // SSI: SSIENR
- mov r1, #0x0
+ // set up quad spi
+ mov r1, #2 // quad spi
lsl r1, r1, #21 // SPI_FRF
- mov r2, #31
+ mov r2, #31 // 32bit data frame
lsl r2, r2, #16 // DFS_32
add r1, r1, r2
- mov r2, #0x0
+ mov r2, #3 // eeprom mode ???
lsl r2, r2, #8 // TMOD
add r1, r1, r2
- str r1, [r3, #0x0] // SSI_CTRLR0
+ str r1, [r0, #0] // SSI: CTRLR0
- mov r1, #0x03 // read command
- lsl r1, r1, #24
+ mov r1, #0 // NDF = 0
+ str r1, [r0, #0x4] // SSI: CTRLR1
+
+ // setup xip
+ mov r1, #4 // 4 dummy clocks
+ lsl r1, r1, #11 // WAIT_CYCLES
mov r2, #2 // 8bit instruction
- lsl r2, r2, #8
+ lsl r2, r2, #8 // INST_L
add r1, r1, r2
- mov r2, #6 // 24bit address length
- lsl r2, r2, #2
+ mov r2, #8 // address + mode bits
+ lsl r2, r2, #2 // ADDR_L
add r1, r1, r2
- ldr r0, =0xf4
- add r0, r0, r3 // SSI_SPI_CTRLR0
- str r1, [r0, #0x0]
+ add r1, r1, #1 // TRANS_TYPE: command: standard, address: quad
+ mov r2, #0xf4
+ str r1, [r0, r2] // SSI: SPI_CTRLR0
+
+ // re-enable spi
+ mov r1, #1
+ str r1, [r0, #0x8] // SSI: SSIENR
+
+ mov r1, #0xeb // fast read quad i/o
+ str r1, [r0, #0x60] // SSI: DR0
+ mov r1, #0xf0 // 0xa0 is for w25q80bv. 0xf0 is for w25q16j
+ str r1, [r0, #0x60] // SSI: DR0
+ bl wait_ssi
+ // I think I need to read rxd-fifo
- mov r1, #0x0
- str r1, [r3, #0x4] // SSI_CTRLR1_OFFSET
+ // disable spi
+ mov r1, #0
+ str r1, [r0, #0x8] // SSI: SSIENR
+ mov r1, #0xf0
+ lsl r1, r1, #24
+ mov r2, #4 // 4 dummy clocks
+ lsl r2, r2, #11 // WAIT_CYCLES
+ add r1, r1, r2
+ mov r2, #0 // no instruction
+ lsl r2, r2, #8 // INST_L
+ add r1, r1, r2
+ mov r2, #8 // 24bit address + 8bit mode
+ lsl r2, r2, #2 // ADDR_L
+ add r1, r1, r2
+ add r1, r1, #2 // TRANS_TYPE: both in quad
+
+ mov r2, #0xf4
+ str r1, [r0, r2] // SSI: SPI_CTRLR0
+
+ // re-enable ssi
mov r1, #1
- str r1, [r3, #0x8] // SSI_SSIENR_OFFSET
+ str r1, [r0, #0x8] // SSI: SSIENR
pop {r0}
cmp r0, #0
@@ -55,12 +149,32 @@ _stage2_boot:
bx r0
vector_into_flash:
ldr r0, =XIP_BASE
- ldr r2, =0x100
- add r0, r0, r2
+ ldr r1, =0x100
+ add r0, r0, r1
ldr r1, =PPB_BASE
- ldr r2, =0xed08 // M0PLUS_VTOR
- add r1, r1, r2
- str r0, [r1, #0x0]
+ ldr r2, =0xed08
+ str r0, [r1, r2] // M0PLUS: VTOR
ldmia r0, {r0, r1}
msr msp, r0
bx r1
+
+wait_ssi:
+ ldr r0, =XIP_SSI_BASE
+ ldr r1, [r0, #0x28] // SSI: SR
+ mov r2, #4 // TFE
+ tst r1, r2
+ beq wait_ssi
+ mov r2, #1 // BUSY
+ tst r1, r2
+ bne wait_ssi
+ bx lr
+
+read_sreg:
+ // I don't understand why dummy byte is needed
+ push {lr}
+ ldr r1, =XIP_SSI_BASE
+ str r0, [r1, #0x60] // SSI: DR0
+ bl wait_ssi
+ ldr r1, =XIP_SSI_BASE
+ ldr r0, [r1, #0x60] // SSI: DR0
+ pop {pc}
diff --git a/boot2/bs2_default.bin b/boot2/bs2_default.bin
Binary files differ.
diff --git a/main.c b/main.c
@@ -3,6 +3,6 @@ main(void)
{
init();
while(1) {
- putchar(getchar());
+ led_p2();
}
}
