commit dcbb7254695fb1161257f98cf94a9222d290f3e0
parent ad828fa5cb67cff591bf73465a54a9cadc57ff8c
Author: Matsuda Kenji <info@mtkn.jp>
Date: Mon, 1 May 2023 09:27:23 +0900
setup uart0
test to be done
Diffstat:
| M | ex2/main.s | | | 34 | +++++++++++++++++++++++++++++++--- |
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/ex2/main.s b/ex2/main.s
@@ -8,12 +8,11 @@ vectors:
.section .text
reset:
- // unreset gpio, pll_sys
- ldr r0, =(1 << 12 | 1 << 5) // pll_sys | io_bank0
+ // unreset gpio, pll_sys, uart0
+ ldr r0, =(1 << 22 | 1 << 12 | 1 << 5) // uart0 | pll_sys | io_bank0
ldr r3, resets_base
ldr r1, atomic_clr
str r0, [r3, r1] // RESETS: RESET
-
unreset_chk:
ldr r1, [r3, #0x8] // RESETS: RESET_DONE
tst r0, r1
@@ -21,6 +20,11 @@ unreset_chk:
// set gpio functions
ldr r3, io_bank0_base
+ mov r0, #2 // uart0
+ mov r1, #0x4
+ str r0, [r3, r1] // IO_BANK0: GPIO0_CTRL
+ mov r1, #0xc
+ str r0, [r3, r1] // IO_BANK0: GPIO1_CTRL
mov r0, #5 // sio
mov r1, #0xc4
str r0, [r3, r1] // IO_BANK0: GPIO24_CTRL
@@ -70,6 +74,26 @@ wait_vco:
ldr r3, clocks_base
ldr r0, =(0x0 << 5 | 0x1)
str r0, [r3, #0x3c] // CLOCKS: CLK_SYS_CTRL
+ // enable clk_peri
+ mov r0, #1
+ lsl r0, r0, #11
+ str r0, [r3, #0x48] // CLOCKS: CLK_PERI_CTRL
+
+ // enable uart0
+ ldr r3, uart0_base
+ ldr r0, =(1 << 9 | 1 << 8 | 1) // RXE | TXE | UARTEN
+ ldr r1, atomic_set
+ add r1, r1, #0x30
+ str r0, [r3, r1] // UART: UARTCR
+ // enable FIFO and set format
+ ldr r0, =(3 << 5 | 1 << 4) // 8bit WLEN | FEN
+ str r0, [r3, #0x2c] // UART: UARTLCR_H
+ // set baudrate 115200
+ // BDRI = 72, BDRF = 0.157 (10 / 64)
+ mov r0, #72
+ str r0, [r3, #0x24] // UART: UARTIBRD
+ mov r0, #10
+ str r0, [r3, #0x28] // UART: UARTFBRD
loop:
bl bled0
@@ -138,6 +162,8 @@ delay_loop:
.align 2
literals:
.ltorg
+atomic_set:
+ .word 0x00002000
atomic_clr:
.word 0x00003000
clocks_base:
@@ -150,5 +176,7 @@ xosc_base:
.word 0x40024000
pll_sys_base:
.word 0x40028000
+uart0_base:
+ .word 0x40034000
sio_base:
.word 0xd0000000
