rp2040

commit ad828fa5cb67cff591bf73465a54a9cadc57ff8c
parent 26b9cb79cba4f70b7123101fea04ed118b6cfd56
Author: Matsuda Kenji <info@mtkn.jp>
Date:   Sat, 29 Apr 2023 09:37:16 +0900

use pll and drive at 133MHz

Diffstat:
M
ex2/main.s
 | 
33
++++++++++++++++++++++++++++-----

1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/ex2/main.s b/ex2/main.s
@@ -8,9 +8,8 @@ vectors:
 
 	.section .text
 reset:
-	// unreset gpio
-	mov r0, #1
-	lsl r0, r0, #5 // io_bank0
+	// unreset gpio, pll_sys
+	ldr r0, =(1 << 12 | 1 << 5) // pll_sys | io_bank0
 	ldr r3, resets_base
 	ldr r1, atomic_clr
 	str r0, [r3, r1] // RESETS: RESET
@@ -45,9 +44,31 @@ wait_xosc:
 	lsr r0, r0, #31 // STABLE bit
 	beq wait_xosc
 
-	// set system clock xosc
+	// setup pll_sys
+	ldr r3, pll_sys_base
+	// set feedback divider
+	mov r0, #133
+	str r0, [r3, #0x8] // PLL: FBDIV_INT
+	// power on pll and vco
+	ldr r0, =(1 << 5 | 1) // VCOPD | PD
+	ldr r1, atomic_clr
+	add r1, r1, #0x4
+	str r0, [r3, r1] // PLL: PWR
+	// wait vco to lock
+wait_vco:
+	ldr r0, [r3, #0] // PLL: CS
+	lsl r0, r0, #31
+	beq wait_vco
+	// setup post dividers
+	ldr r0, =(4 << 16 | 3 << 12)
+	str r0, [r3, #0xc] // PLL: PRIM
+	// power on post divider
+	mov r0, #8 // POSTDIVPD
+	str r0, [r3, r1] // PLL: PWR
+
+	// set system clock clksrc_pll_sys
 	ldr r3, clocks_base
-	ldr r0, =(0x3 << 5 | 0x1)
+	ldr r0, =(0x0 << 5 | 0x1)
 	str r0, [r3, #0x3c] // CLOCKS: CLK_SYS_CTRL
 
 loop:
@@ -127,5 +148,7 @@ io_bank0_base:
 	.word 0x40014000
 xosc_base:
 	.word 0x40024000
+pll_sys_base:
+	.word 0x40028000
 sio_base:
 	.word 0xd0000000