commit d631538bf79ac256e65bfa9b3e1f8432aa03303a
parent eff07034c7559d6e7008df62f86bef8c677a11f2
Author: Matsuda Kenji <info@mtkn.jp>
Date: Thu, 6 Apr 2023 08:40:27 +0900
change register
Diffstat:
| M | boot2/boot2.S | | | 70 | +++++++++++++++++++++++++++++++++++----------------------------------- |
1 file changed, 35 insertions(+), 35 deletions(-)
diff --git a/boot2/boot2.S b/boot2/boot2.S
@@ -7,58 +7,57 @@
.equ PPB_BASE, 0xe0000000
boot2:
- push {lr}
+ push {r4, lr}
- ldr r0, =PADS_QSPI_BASE
+ ldr r4, =PADS_QSPI_BASE
ldr r1, =(2 << 4 | 1) // 8mA, slew fast
- str r1, [r0, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
+ str r1, [r4, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
- ldr r0, =XIP_SSI_BASE
+ // r4 should not be changed
+ ldr r4, =XIP_SSI_BASE
// set SSI standard SPI
// disable ssi
mov r1, #0
- str r1, [r0, #0x8] // SSI: SSIENR
+ str r1, [r4, #0x8] // SSI: SSIENR
//set divider
ldr r1, =0x2 // This is 2 in sdk
- str r1, [r0, #0x14] // SSI: BAUDR
+ str r1, [r4, #0x14] // SSI: BAUDR
// set 1-cycle sample delay.
mov r1, #1
mov r2, #0xf0
- str r1, [r0, r2] // SSI: RX_SAMPLE_DLY
+ str r1, [r4, r2] // SSI: RX_SAMPLE_DLY
// setup sregs
ldr r1, =((7 << 16) | (0 << 8)) // 8bit data frame size, tx and rx
- str r1, [r0, #0] // SSI: CTRLR0
+ str r1, [r4, #0] // SSI: CTRLR0
// enable ssi
mov r1, #1
- str r1, [r0, #0x8] // SSI: SSIENR
+ str r1, [r4, #0x8] // SSI: SSIENR
// set flash QSPI
// write enable
mov r1, #0x06 // write enable
- str r1, [r0, #0x60] // SSI: DR0
+ str r1, [r4, #0x60] // SSI: DR0
bl wait_ssi
- ldr r0, =XIP_SSI_BASE
- ldr r1, [r0, #0x60] // SSI: DR0
+ ldr r1, [r4, #0x60] // SSI: DR0
// set sreg
mov r1, #0x31 // write status register-2
- str r1, [r0, #0x60] // SSI: DR0
+ str r1, [r4, #0x60] // SSI: DR0
mov r1, #0x2 // quad enable
- str r1, [r0, #0x60] // SSI: DR0
+ str r1, [r4, #0x60] // SSI: DR0
bl wait_ssi
- ldr r1, [r0, #0x60] // SSI: DR0
- ldr r1, [r0, #0x60] // SSI: DR0
+ ldr r1, [r4, #0x60] // SSI: DR0
+ ldr r1, [r4, #0x60] // SSI: DR0
wait_sreg:
mov r1, #0x5 // read status register-1
// maybe the first str represents the command
// while does the second one the address.
- str r1, [r0, #0x60] // SSI: DR0
- str r1, [r0, #0x60] // SSI: DR0
+ str r1, [r4, #0x60] // SSI: DR0
+ str r1, [r4, #0x60] // SSI: DR0
bl wait_ssi
- ldr r0, =XIP_SSI_BASE
- ldr r1, [r0, #0x60] // SSI: DR0
- ldr r1, [r0, #0x60] // SSI: DR0
+ ldr r1, [r4, #0x60] // SSI: DR0
+ ldr r1, [r4, #0x60] // SSI: DR0
mov r2, #1 // BUSY flag
tst r1, r2
bne wait_sreg
@@ -66,47 +65,48 @@ wait_sreg:
// set SSI QSPI and XIP
// disable ssi
mov r1, #0
- str r1, [r0, #0x8] // SSI: SSIENR
+ str r1, [r4, #0x8] // SSI: SSIENR
// set up quad spi
ldr r1, =((2 << 21) | (31 << 16)| (0 << 8)) // tmod is 3 in sdk
- str r1, [r0, #0] // SSI: CTRLR0
+ str r1, [r4, #0] // SSI: CTRLR0
mov r1, #0 // NDF = 0
- str r1, [r0, #0x4] // SSI: CTRLR1
+ str r1, [r4, #0x4] // SSI: CTRLR1
// setup xip
ldr r1, =((4 << 11) | (2 << 8) | (8 << 2) | (1 << 0))
mov r2, #0xf4
- str r1, [r0, r2] // SSI: SPI_CTRLR0
+ str r1, [r4, r2] // SSI: SPI_CTRLR0
// re-enable spi
mov r1, #1
- str r1, [r0, #0x8] // SSI: SSIENR
+ str r1, [r4, #0x8] // SSI: SSIENR
// first read from flash
// set flash continuous read
mov r1, #0xeb // fast read quad i/o
- str r1, [r0, #0x60] // SSI: DR0
+ str r1, [r4, #0x60] // SSI: DR0
// continuous read is not documented in w25q16j datasheet...
// it says mode bits shoud be Fxh (x: don't care)...
// in w2580bv datasheet, these bits are said to be 0bxx10xxxx.
// why w25q16j lacks the description?
mov r1, #0x20
- str r1, [r0, #0x60] // SSI: DR0
+ str r1, [r4, #0x60] // SSI: DR0
bl wait_ssi
// I think I need to read rxd-fifo
- // ldr r1, [r0, #0x60]
+ // ldr r1, [r4, #0x60]
// set SIP continuous read
- // disable spi
+ // disable ssi
mov r1, #0
- str r1, [r0, #0x8] // SSI: SSIENR
+ str r1, [r4, #0x8] // SSI: SSIENR
// the command bit is not documented.
ldr r1, =((0x20 << 24) | (4 << 11) | (0 << 8) | (8 << 2) | (2 << 0))
mov r2, #0xf4
- str r1, [r0, r2] // SSI: SPI_CTRLR0
+ str r1, [r4, r2] // SSI: SPI_CTRLR0
// re-enable ssi
mov r1, #1
- str r1, [r0, #0x8] // SSI: SSIENR
+ str r1, [r4, #0x8] // SSI: SSIENR
// exit from boot2
+ pop {r4}
pop {r0}
cmp r0, #0
beq vector_into_flash
@@ -120,8 +120,8 @@ vector_into_flash:
bx r1
wait_ssi:
- ldr r0, =XIP_SSI_BASE
- ldr r1, [r0, #0x28] // SSI: SR
+ // asumes that r4 is XIP_SSI_BASE
+ ldr r1, [r4, #0x28] // SSI: SR
mov r2, #4 // TFE
tst r1, r2
beq wait_ssi
