commit b663eab7de673564012abdc697b880683c1208d2
parent ce2125ad05e2d3ff10e5cc8bfd7db7739a888004
Author: Matsuda Kenji <info@mtkn.jp>
Date: Wed, 22 Mar 2023 11:08:02 +0900
fix something. something weird.
Diffstat:
| M | main.s | | | 41 | +++++++++++++++++++++-------------------- |
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/main.s b/main.s
@@ -1,7 +1,7 @@
.section .text
.global main
main:
- // reset gpio and pll_sys
+ // unreset gpio and pll_sys and uart0
mov r1, #1
lsl r0, r1, #5 // io_bank0
lsl r1, r1, #12 // pll_sys
@@ -13,8 +13,8 @@ main:
// set gpio functions
ldr r0, io_bank0_base
- mov r1, #2
- mov r2, #5
+ mov r1, #2 // uart0
+ mov r2, #5 // sio
add r0, r0, #0x64 // io_bank0_gpio12_ctrl
str r1, [r0, #0] // uart0
add r0, r0, #0x8 // #0x6c io_bank0_gpio13_ctrl
@@ -92,7 +92,7 @@ pll_lock:
// enable clk_peri
lsl r1, r1, #11
str r1, [r0, #0x48]
-
+
// enable uart0
ldr r0, uart0_base
mov r1, #1
@@ -106,12 +106,8 @@ pll_lock:
mov r1, #52
str r1, [r0, #0x28] // UART0_UARTFBRD
// setup uart0
- mov r1, #2 // WLEN = 2
- lsl r1, r1, #3
- add r1, r1, #1 // ESP = 1 (even parity)
- lsl r1, r1, #1
- add r1, r1, #1 // PEN
- lsl r1, r1, #1
+ mov r1, #3 // WLEN = 8
+ lsl r1, r1, #5
str r1, [r0, #0x2c] // UART0_UARTLCR_H
loop:
@@ -143,16 +139,19 @@ reset_chk:
bx lr
uart0_write:
- mov r1, #0xFF
- and r0, r0, r1
- ldr r1, uart0_base
- mov r2, #32
+ push {lr}
+ push {r4, r5, r6, r7}
+ mov r4, #0xFF
+ and r4, r4, r0
+ ldr r5, uart0_base
+ mov r6, #32
uart0_txff:
- ldr r3, [r1, #0x18] // UART0_UARTFR
- and r3, r3, r2
+ ldr r7, [r5, #0x18] // UART0_UARTFR
+ and r7, r7, r6
bne uart0_txff
- str r0, [r1, #0] // UART0_UARTDR
- bx lr
+ str r4, [r5, #0] // UART0_UARTDR
+ pop {r4, r5, r6, r7}
+ pop {pc}
uart0_read:
ldr r1, uart0_base
@@ -204,14 +203,16 @@ p1:
led_blink:
push {lr}
- push {r4}
+ push {r4, r5}
ldr r4, sio_base
mov r5, r0
+ push {r5}
str r5, [r4, #0x10] // SIO_GPIO_OUT_SET
bl delay
+ pop {r5}
str r5, [r4, #0x18] // SIO_GPIO_OUT_CLR
bl delay
- pop {r4}
+ pop {r4, r5}
pop {pc}
delay:
