commit ce2125ad05e2d3ff10e5cc8bfd7db7739a888004
parent 758fcb6332fb119f5f036459bb5c4179ad85d157
Author: Matsuda Kenji <info@mtkn.jp>
Date: Wed, 22 Mar 2023 09:24:47 +0900
add uart read/write. something wrong
Diffstat:
M | main.s | | | 27 | ++++++++++++++++++++++++++- |
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/main.s b/main.s
@@ -115,7 +115,8 @@ pll_lock:
str r1, [r0, #0x2c] // UART0_UARTLCR_H
loop:
- bl p0
+ bl uart0_read
+ bl uart0_write
b loop
// functions
@@ -141,6 +142,30 @@ reset_chk:
beq reset_chk
bx lr
+uart0_write:
+ mov r1, #0xFF
+ and r0, r0, r1
+ ldr r1, uart0_base
+ mov r2, #32
+uart0_txff:
+ ldr r3, [r1, #0x18] // UART0_UARTFR
+ and r3, r3, r2
+ bne uart0_txff
+ str r0, [r1, #0] // UART0_UARTDR
+ bx lr
+
+uart0_read:
+ ldr r1, uart0_base
+ mov r2, #16
+uart0_rxfe:
+ ldr r3, [r1, #0x18] // UART0_UARTFR
+ and r3, r3, r2
+ bne uart0_rxfe
+ ldr r0, [r1, #0] // UART0_UARTDR
+ mov r1, #0xFF
+ and r0, r0, r1
+ bx lr
+
pr:
// print register
push {lr}