commit 662ac5be23ee6c63c9b358e25d9dc3c2c50ca304
parent 181ef24e87dc72c878c65494a07c284daf688276
Author: Matsuda Kenji <info@mtkn.jp>
Date: Wed, 28 Feb 2024 08:02:11 +0900
move uart0 unreset after enabling clock_peri
Diffstat:
| M | ex3/main.s | | | 34 | ++++++++++++---------------------- |
1 file changed, 12 insertions(+), 22 deletions(-)
diff --git a/ex3/main.s b/ex3/main.s
@@ -23,8 +23,8 @@ vectors:
.section .text
reset:
- // unreset gpio, pll_sys, timer, uart0
- ldr r0, =(1 << 22 | 1 << 21 | 1 << 12 | 1 << 5) // uart0 | timer | pll_sys | io_bank0
+ // unreset gpio, pll_sys, timer
+ ldr r0, =(1 << 21 | 1 << 12 | 1 << 5) // | timer | pll_sys | io_bank0
ldr r3, resets_base
ldr r1, atomic_clr
str r0, [r3, r1] // RESETS: RESET
@@ -90,6 +90,16 @@ wait_vco:
mov r0, #0x2
str r0, [r3, #0x30] // CLOCKS: CLK_REF_CTRL
+ // unreset uart0
+ ldr r0, =(1 << 22)
+ ldr r3, resets_base
+ ldr r1, atomic_clr
+ str r0, [r3, r1] // RESETS: RESET
+unreset_chk1:
+ ldr r1, [r3, #0x8] // RESETS: RESET_DONE
+ bic r0, r1
+ bne unreset_chk1
+
// disable rosc
ldr r3, rosc_base
ldr r0, =0xd1e000
@@ -128,26 +138,6 @@ wait_vco:
ldr r0, =0x20000 //
bl set_alarm
- // debug: count frequency
- ldr r3, clocks_base
- add r3, r3, #0x80
-wait_fc0:
- ldr r0, [r3, #0x18] // CLOCKS: FC0_STATUS
- ldr r1, =(1 << 8) // RUNNING
- tst r0, r1
- bne wait_fc0
- ldr r0, =(12 * 1000) // 12MHz
- str r0, [r3, #0] // CLOCKS: FC0_REF_KHZ
- mov r0, #0x0a // clk_peri
- str r0, [r3, #0x14] // CLOCKS: FC0_SRC
-wait_fc1:
- ldr r0, [r3, #0x18] // CLOCKS: FC0_STATUS
- ldr r1, =(1 << 4) // DONE
- tst r0, r1
- beq wait_fc1
- ldr r0, [r3, #0x1c] // CLOCKS: FC0_RESULT
- bl printh
-
loop:
ldr r0, =0xdeadcafe
bl printh
