rp2040

commit 3fc845014151d81177df9ca33d215418cc2f3611
parent 3d4cfb0330b4d9e4f8caf211a974a40e0755e89b
Author: Matsuda Kenji <info@mtkn.jp>
Date:   Wed, 22 Mar 2023 07:45:25 +0900

set clock frequency to 125MHz

Diffstat:
M
main.s
 | 
4
++--

1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/main.s b/main.s
@@ -45,7 +45,7 @@ xosc_stable:
 
 	// set pll feedback divider
 	ldr r0, pll_sys_base
-	mov r1, #16
+	mov r1, #125
 	str r1, [r0, #0x8] // PLL_FBDIV_INT
 
 	// power on pll
@@ -65,7 +65,7 @@ pll_lock:
 	ldr r0, pll_sys_base
 	ldr r1, atomic_clr
 	add r0, r0, r1
-	mov r1, #4
+	mov r1, #3
 	lsl r1, r1, #4
 	add r1, r1, #4
 	lsl r1, r1, #12