commit 3d4cfb0330b4d9e4f8caf211a974a40e0755e89b
parent 760b82e3729aa5b63e3d8001c799e9191a204e77
Author: Matsuda Kenji <info@mtkn.jp>
Date: Tue, 21 Mar 2023 12:14:57 +0900
PLL worked.
But I don't understand why pll post dividers shoud be set atomically.
And I don't understand how to push and pop registers.
It makes some warning and pico stops suddenly.
Maybe stack overflows.
Diffstat:
| M | main.s | | | 24 | ++++++++++++------------ |
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/main.s b/main.s
@@ -45,8 +45,7 @@ xosc_stable:
// set pll feedback divider
ldr r0, pll_sys_base
- mov r1, #0x4
- lsl r1, r1, #4 //
+ mov r1, #16
str r1, [r0, #0x8] // PLL_FBDIV_INT
// power on pll
@@ -63,11 +62,12 @@ pll_lock:
beq pll_lock
// set post dividers
- ldr r1, atomic_set
+ ldr r0, pll_sys_base
+ ldr r1, atomic_clr
add r0, r0, r1
- mov r1, #1
+ mov r1, #4
lsl r1, r1, #4
- add r1, r1, #1
+ add r1, r1, #4
lsl r1, r1, #12
str r1, [r0, #0xc] // PLL_PRIM
@@ -83,11 +83,9 @@ pll_lock:
mov r1, #1
str r1, [r0, #0x3c] // CLOCKS_CLK_SYS_CTRL
- ldr r1, pll_sys_base
- ldr r0, [r1, #0x4]
- bl pr
-
loop:
+ bl p0
+ bl p1
b loop
// functions
@@ -150,18 +148,20 @@ p1:
pop {pc}
led_blink:
- push {lr, r4}
+ push {lr}
+ push {r4}
ldr r4, sio_base
mov r5, r0
str r5, [r4, #0x10] // SIO_GPIO_OUT_SET
bl delay
str r5, [r4, #0x18] // SIO_GPIO_OUT_CLR
bl delay
- pop {r4, pc}
+ pop {r4}
+ pop {pc}
delay:
mov r0, #1
- lsl r0, r0, #20
+ lsl r0, r0, #21
del_loop:
sub r0, r0, #1
bne del_loop
