rp2040

commit 3d432a5de3799a43fd02655bf999fc4f0c04d07f
parent b8dae75bdba0ea48543f3d84381597ebf8da2bad
Author: Matsuda Kenji <info@mtkn.jp>
Date:   Mon, 17 Apr 2023 10:25:51 +0900

update license

Diffstat:
M
License
 | 
26
+-------------------------
D
boot2_qspi.s
 | 
171
-------------------------------------------------------------------------------
D
boot2_sram.s
 | 
152
-------------------------------------------------------------------------------

3 files changed, 1 insertion(+), 348 deletions(-)
diff --git a/License b/License
@@ -1,26 +1,2 @@
 2023 Matsuda Kenji <info@mtkn.jp>
-Public Domain excepting the following files
-
-boot2.s:
-Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following
-   disclaimer.
-
-2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
-   disclaimer in the documentation and/or other materials provided with the distribution.
-
-3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products
-   derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+Public Domain
diff --git a/boot2_qspi.s b/boot2_qspi.s
@@ -1,171 +0,0 @@
-// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
-// SPDX-License-Identifier: BSD-3-Clause
-
-.cpu cortex-m0plus
-.thumb
-
-	.section .boot2
-	.global setup_xip
-	.thumb_func
-setup_xip:
-	push {r4, lr}
-
-	// setup QSPI pad
-	ldr r4, pads_qspi_base
-	ldr r1, =(0 << 4 | 0 << 1 | 1) // 2mA, schmitt off, slew fast
-	str r1, [r4, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
-
-	// r4 should not be changed from this point on
-	ldr r4, xip_ssi_base
-
-	// set SSI standard SPI
-	// disable SSI
-	mov r1, #0
-	str r1, [r4, #0x8] // SSI: SSIENR
-	//set divider
-	mov r1, #0x2
-	str r1, [r4, #0x14] // SSI: BAUDR
-	// set 1-cycle sample delay.
-	mov r1, #1
-	mov r2, #0xf0
-	str r1, [r4, r2] // SSI: RX_SAMPLE_DLY
-	// setup SSI
-	ldr r1, =(7 << 16 | 3 << 8) // 8bit data frame size, eeprom
-	str r1, [r4, #0] // SSI: CTRLR0
-	mov r1, #0 // NDF = 0
-	str r1, [r4, #0x4] // SSI: CTRLR1
-	// enable SSI
-	mov r1, #1
-	str r1, [r4, #0x8] // SSI: SSIENR
-
-	// set flash QSPI
-	// write enable
-	mov r1, #0x06 // write enable
-	str r1, [r4, #0x60] // SSI: DR0
-	bl wait_ssi
-	ldr r1, [r4, #0x60] // SSI: DR0
-	// enable QSPI
-	mov r1, #0x31 // write status register-2
-	str r1, [r4, #0x60] // SSI: DR0
-	mov r1, #0x2 // quad enable
-	str r1, [r4, #0x60] // SSI: DR0
-	bl wait_ssi
-	ldr r1, [r4, #0x60] // SSI: DR0
-	ldr r1, [r4, #0x60] // SSI: DR0
-
-wait_sreg:
-	mov r1, #0x5 // read status register-1
-	// This str is required twice if TMOD = 0.
-	// In this case, /CS signal is set to high just
-	// after the first str instruction and the flash
-	// doesn't shift out the status register.
-	// On the other hand, If TMOD = 3 (eeprom),
-	// then the /CS is kept to low until NDF + 1
-	// data frames are captured.
-	// Shiran Kedo.
-	str r1, [r4, #0x60] // SSI: DR0
-	bl wait_ssi
-	ldr r1, [r4, #0x60] // SSI: DR0
-	mov r2, #1 // BUSY flag
-	tst r1, r2
-	bne wait_sreg
-
-	// set SSI QSPI and XIP
-	// disable SSI
-	mov r1, #0
-	str r1, [r4, #0x8] // SSI: SSIENR
-	// set up QSPI
-	// DFS is said to be the number of clocks of a data frame - 1.
-	// But in QSPI mode, a frame is 32 bits and is transfered in 8 clocks.
-	// However, if DFS is set to 7, It doesn't work.
-	// Maybe this is a bug of the documentation.
-	ldr r1, =(2 << 21 | 31 << 16 | 3 << 8) // quad, 32bit data frame, eeprom
-	str r1, [r4, #0] // SSI: CTRLR0
-	// setup xip
-	ldr r1, =(4 << 11 | 2 << 8 | 8 << 2 | 1 << 0)
-	mov r2, #0xf4
-	str r1, [r4, r2] // SSI: SPI_CTRLR0
-	// re-enable SSI
-	mov r1, #1
-	str r1, [r4, #0x8] // SSI: SSIENR
-
-	// first read from flash
-	// set flash continuous read
-	mov r1, #0xeb // fast read quad i/o
-	str r1, [r4, #0x60] // SSI: DR0
-	// continuous read is not documented in w25q16j datasheet...
-	// it says mode bits should be Fxh (x: don't care)...
-	// in w2580bv datasheet, these bits are said to be 0bxx10xxxx.
-	// why w25q16j lacks the description?
-	mov r1, #0x20
-	str r1, [r4, #0x60] // SSI: DR0
-	bl wait_ssi
-
-	// set SIP continuous read
-	// disable SSI
-	mov r1, #0
-	str r1, [r4, #0x8] // SSI: SSIENR
-	// the command bit is not documented.
-	ldr r1, =(0x20 << 24 | 4 << 11 | 0 << 8 | 8 << 2 | 2 << 0)
-	mov r2, #0xf4
-	str r1, [r4, r2] // SSI: SPI_CTRLR0
-	// re-enable SSI
-	mov r1, #1
-	str r1, [r4, #0x8] // SSI: SSIENR
-
-	// this code should be rewritten using dma.
-	ldr r2, boot2_end
-	ldr r3, sram_base
-	ldr r0, etext
-	sub r0, r0, r3
-	lsr r0, #2
-sram_cpy:
-	ldr r1, [r2, #0]
-	str r1, [r3, #0]
-	add r2, r2, #0x4
-	add r3, r3, #0x4
-	sub r0, r0, #0x1
-	bne sram_cpy
-
-	// exit from boot2
-	pop {r4}
-	pop {r0}
-	cmp r0, #0
-	beq initial_boot
-	bx r0
-initial_boot:
-	ldr r0, sram_base
-	ldr r1, m0plus_vtor 
-	str r0, [r1, #0] // M0PLUS: VTOR
-	ldr r1, [r0, #4] // entry point
-	ldr r0, [r0, #0] // stack pointer
-	mov sp, r0
-	bx r1
-
-wait_ssi:
-	// asumes that r4 is xip_ssi_base
-	ldr r1, [r4, #0x28] // SSI: SR
-	mov r2, #4 // TFE
-	tst r1, r2
-	beq wait_ssi
-	mov r2, #1 // BUSY
-	tst r1, r2
-	bne wait_ssi
-	bx lr
-
-	.align 2
-boot2_end:
-	.word 0x10000000 + 0x100
-xip_ssi_base:
-	.word 0x18000000
-sram_base:
-	.word 0x20000000
-pads_qspi_base:
-	.word 0x40020000
-m0plus_vtor:
-	.word 0xe0000000 + 0xed08
-etext:
-	.word _etext
-literals:
-	.ltorg
-
diff --git a/boot2_sram.s b/boot2_sram.s
@@ -1,152 +0,0 @@
-// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
-// SPDX-License-Identifier: BSD-3-Clause
-
-.cpu cortex-m0plus
-.thumb
-
-	.section .boot2
-	.global setup_ssi
-	.thumb_func
-setup_ssi:
-	push {r4, r5, r6, r7, lr}
-
-	// setup QSPI pad
-	ldr r4, pads_qspi_base
-	ldr r1, =(0 << 4 | 0 << 1 | 1) // 2mA, schmitt off, slew fast
-	str r1, [r4, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
-
-	// r4 should not be changed from this point on
-	ldr r4, xip_ssi_base
-
-	// set SSI standard SPI
-	// disable SSI
-	mov r1, #0
-	str r1, [r4, #0x8] // SSI: SSIENR
-	//set divider
-	mov r1, #0x2
-	str r1, [r4, #0x14] // SSI: BAUDR
-	// set 1-cycle sample delay.
-	mov r1, #1
-	mov r2, #0xf0
-	str r1, [r4, r2] // SSI: RX_SAMPLE_DLY
-	// setup SSI
-	ldr r1, =(7 << 16 | 3 << 8) // 8bit data frame size, eeprom
-	str r1, [r4, #0] // SSI: CTRLR0
-	mov r1, #0 // NDF = 0
-	str r1, [r4, #0x4] // SSI: CTRLR1
-	// enable SSI
-	mov r1, #1
-	str r1, [r4, #0x8] // SSI: SSIENR
-
-	// set flash QSPI
-	// write enable
-	mov r1, #0x06 // write enable
-	str r1, [r4, #0x60] // SSI: DR0
-	bl wait_ssi
-	ldr r1, [r4, #0x60] // SSI: DR0
-	// enable QSPI
-	mov r1, #0x31 // write status register-2
-	str r1, [r4, #0x60] // SSI: DR0
-	mov r1, #0x2 // quad enable
-	str r1, [r4, #0x60] // SSI: DR0
-	bl wait_ssi
-	ldr r1, [r4, #0x60] // SSI: DR0
-	ldr r1, [r4, #0x60] // SSI: DR0
-wait_sreg:
-	mov r1, #0x5 // read status register-1
-	// This str is required twice if TMOD = 0.
-	// In this case, /CS signal is set to high just
-	// after the first str instruction and the flash
-	// doesn't shift out the status register.
-	// On the other hand, If TMOD = 3 (eeprom),
-	// then the /CS is kept to low until NDF + 1
-	// data frames are captured.
-	// Shiran Kedo.
-	str r1, [r4, #0x60] // SSI: DR0
-	bl wait_ssi
-	ldr r1, [r4, #0x60] // SSI: DR0
-	mov r2, #1 // BUSY flag
-	tst r1, r2
-	bne wait_sreg
-
-	// set SSI QSPI
-	// disable SSI
-	mov r1, #0
-	str r1, [r4, #0x8] // SSI: SSIENR
-	// set up QSPI
-	// DFS is said to be the number of clocks of a data frame - 1.
-	// But in QSPI mode, a frame is 32 bits and is transfered in 8 clocks.
-	// However, if DFS is set to 7, It doesn't work.
-	// Maybe this is a bug of the documentation.
-	ldr r1, =(2 << 21 | 31 << 16 | 3 << 8) // quad, 32bit data frame, eeprom
-	str r1, [r4, #0] // SSI: CTRLR0
-	ldr r1, =(4 << 11 | 2 << 8 | 6 << 2 | 1 << 0)
-	mov r2, #0xf4
-	str r1, [r4, r2] // SSI: SPI_CTRLR0
-	// re-enable SSI
-	mov r1, #1
-	str r1, [r4, #0x8] // SSI: SSIENR
-
-	// this code should be rewritten using dma.
-	mov r5, #0xeb
-	lsl r5, r5, #24
-	ldr r6, boot2_end
-	lsl r6, r6, #8
-	lsr r6, r6, #8
-	add r5, r5, r6 // flash read command
-	ldr r6, sram_base // sram dst address
-	ldr r7, etext
-	sub r7, r0, r3
-	lsr r7, #2  // counter
-sram_cpy:
-	str r5, [r4, #0x60] // SSI: DR0
-	bl wait_ssi
-	ldr r0, [r4, #0x60] // SSI: DR0
-	str r0, [r6, #0]
-	add r5, r5, #0x4
-	add r6, r6, #0x4
-	sub r7, r7, #0x1
-	bne sram_cpy
-
-	// exit from boot2
-	pop {r4, r5, r6, r7}
-	pop {r0}
-	cmp r0, #0
-	beq initial_boot
-	bx r0
-initial_boot:
-	ldr r0, sram_base
-	ldr r1, m0plus_vtor 
-	str r0, [r1, #0] // M0PLUS: VTOR
-	ldr r1, [r0, #4] // entry point
-	ldr r0, [r0, #0] // stack pointer
-	mov sp, r0
-	bx r1
-
-wait_ssi:
-	// asumes that r4 is xip_ssi_base
-	ldr r1, [r4, #0x28] // SSI: SR
-	mov r2, #4 // TFE
-	tst r1, r2
-	beq wait_ssi
-	mov r2, #1 // BUSY
-	tst r1, r2
-	bne wait_ssi
-	bx lr
-
-	.align 2
-boot2_end:
-	.word 0x10000000 + 0x100
-xip_ssi_base:
-	.word 0x18000000
-sram_base:
-	.word 0x20000000
-pads_qspi_base:
-	.word 0x40020000
-m0plus_vtor:
-	.word 0xe0000000 + 0xed08
-etext:
-	.word _etext
-literals:
-	.ltorg
-