commit b8dae75bdba0ea48543f3d84381597ebf8da2bad
parent 7e41616cc04dd6d4f4bdc71ca0dda065a4cf89dd
Author: Matsuda Kenji <info@mtkn.jp>
Date: Mon, 17 Apr 2023 10:24:49 +0900
use rom func for boot2
Diffstat:
3 files changed, 13 insertions(+), 115 deletions(-)
diff --git a/boot2.s b/boot2.s
@@ -1,6 +1,3 @@
-// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
-// SPDX-License-Identifier: BSD-3-Clause
-
.cpu cortex-m0plus
.thumb
@@ -15,103 +12,13 @@ setup_xip:
ldr r1, =(0 << 4 | 0 << 1 | 1) // 2mA, schmitt off, slew fast
str r1, [r4, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
- // r4 should not be changed from this point on
- ldr r4, xip_ssi_base
-
- // set SSI standard SPI
- // disable SSI
- mov r1, #0
- str r1, [r4, #0x8] // SSI: SSIENR
- //set divider
- mov r1, #0x2
- str r1, [r4, #0x14] // SSI: BAUDR
- // set 1-cycle sample delay.
- mov r1, #1
- mov r2, #0xf0
- str r1, [r4, r2] // SSI: RX_SAMPLE_DLY
- // setup SSI
- ldr r1, =(7 << 16 | 3 << 8) // 8bit data frame size, eeprom
- str r1, [r4, #0] // SSI: CTRLR0
- mov r1, #0 // NDF = 0
- str r1, [r4, #0x4] // SSI: CTRLR1
- // enable SSI
- mov r1, #1
- str r1, [r4, #0x8] // SSI: SSIENR
-
- // set flash QSPI
- // write enable
- mov r1, #0x06 // write enable
- str r1, [r4, #0x60] // SSI: DR0
- bl wait_ssi
- ldr r1, [r4, #0x60] // SSI: DR0
- // enable QSPI
- mov r1, #0x31 // write status register-2
- str r1, [r4, #0x60] // SSI: DR0
- mov r1, #0x2 // quad enable
- str r1, [r4, #0x60] // SSI: DR0
- bl wait_ssi
- ldr r1, [r4, #0x60] // SSI: DR0
- ldr r1, [r4, #0x60] // SSI: DR0
-
-wait_sreg:
- mov r1, #0x5 // read status register-1
- // This str is required twice if TMOD = 0.
- // In this case, /CS signal is set to high just
- // after the first str instruction and the flash
- // doesn't shift out the status register.
- // On the other hand, If TMOD = 3 (eeprom),
- // then the /CS is kept to low until NDF + 1
- // data frames are captured.
- // Shiran Kedo.
- str r1, [r4, #0x60] // SSI: DR0
- bl wait_ssi
- ldr r1, [r4, #0x60] // SSI: DR0
- mov r2, #1 // BUSY flag
- tst r1, r2
- bne wait_sreg
+ ldr r4, rom_base
- // set SSI QSPI and XIP
- // disable SSI
- mov r1, #0
- str r1, [r4, #0x8] // SSI: SSIENR
- // set up QSPI
- // DFS is said to be the number of clocks of a data frame - 1.
- // But in QSPI mode, a frame is 32 bits and is transfered in 8 clocks.
- // However, if DFS is set to 7, It doesn't work.
- // Maybe this is a bug of the documentation.
- ldr r1, =(2 << 21 | 31 << 16 | 3 << 8) // quad, 32bit data frame, eeprom
- str r1, [r4, #0] // SSI: CTRLR0
- // setup xip
- ldr r1, =(4 << 11 | 2 << 8 | 8 << 2 | 1 << 0)
- mov r2, #0xf4
- str r1, [r4, r2] // SSI: SPI_CTRLR0
- // re-enable SSI
- mov r1, #1
- str r1, [r4, #0x8] // SSI: SSIENR
-
- // first read from flash
- // set flash continuous read
- mov r1, #0xeb // fast read quad i/o
- str r1, [r4, #0x60] // SSI: DR0
- // continuous read is not documented in w25q16j datasheet...
- // it says mode bits should be Fxh (x: don't care)...
- // in w2580bv datasheet, these bits are said to be 0bxx10xxxx.
- // why w25q16j lacks the description?
- mov r1, #0x20
- str r1, [r4, #0x60] // SSI: DR0
- bl wait_ssi
-
- // set SIP continuous read
- // disable SSI
- mov r1, #0
- str r1, [r4, #0x8] // SSI: SSIENR
- // the command bit is not documented.
- ldr r1, =(0x20 << 24 | 4 << 11 | 0 << 8 | 8 << 2 | 2 << 0)
- mov r2, #0xf4
- str r1, [r4, r2] // SSI: SPI_CTRLR0
- // re-enable SSI
- mov r1, #1
- str r1, [r4, #0x8] // SSI: SSIENR
+ ldrh r0, [r4, #0x14] // rom_func_table
+ ldr r1, =('C' | 'X' << 8) // _flash_enter_cmd_xip()
+ ldrh r2, [r4, #0x18] // rom_table_lookup
+ blx r2
+ blx r0
// this code should be rewritten using dma.
ldr r2, boot2_end
@@ -142,18 +49,9 @@ initial_boot:
mov sp, r0
bx r1
-wait_ssi:
- // asumes that r4 is xip_ssi_base
- ldr r1, [r4, #0x28] // SSI: SR
- mov r2, #4 // TFE
- tst r1, r2
- beq wait_ssi
- mov r2, #1 // BUSY
- tst r1, r2
- bne wait_ssi
- bx lr
-
.align 2
+rom_base:
+ .word 0x00000000
boot2_end:
.word 0x10000000 + 0x100
xip_ssi_base:
diff --git a/boot2.s b/boot2_qspi.s
diff --git a/mach.s b/mach.s
@@ -142,19 +142,19 @@ flash_operation:
ldr r4, rom_base
ldrh r0, [r4, #0x14] // rom_func_table
- ldr r1, =('I' | 'F' << 8) // connect_internal_flash()
+ ldr r1, =('I' | 'F' << 8) // _connect_internal_flash()
ldrh r2, [r4, #0x18] // rom_table_lookup
blx r2
blx r0
ldrh r0, [r4, #0x14] // rom_func_table
- ldr r1, =('E' | 'X' << 8) // exit_xip()
+ ldr r1, =('E' | 'X' << 8) // _flash_exit_xip()
ldrh r2, [r4, #0x18] // rom_table_lookup
blx r2
blx r0
ldrh r0, [r4, #0x14] // rom_func_table
- ldr r1, =('R' | 'E' << 8) // connect_internal_flash
+ ldr r1, =('R' | 'E' << 8) // _flash_range_erase()
ldrh r2, [r4, #0x18] // rom_table_lookup
blx r2
mov r5, r0
@@ -166,13 +166,13 @@ flash_operation:
blx r5
ldrh r0, [r4, #0x14] // rom_func_table
- ldr r1, =('F' | 'C' << 8) // connect_internal_flash
+ ldr r1, =('F' | 'C' << 8) // _flash_flush_cache()
ldrh r2, [r4, #0x18] // rom_table_lookup
blx r2
blx r0
ldrh r0, [r4, #0x14] // rom_func_table
- ldr r1, =('C' | 'X' << 8) // connect_internal_flash
+ ldr r1, =('C' | 'X' << 8) // _flash_enter_cmd_xip()
ldrh r2, [r4, #0x18] // rom_table_lookup
blx r2
blx r0
