commit 241b3584574db84a622a448f0939d36b8eff7f14
parent dc97c51612c9f10fbd30710e2001ecb25ad40556
Author: Matsuda Kenji <info@mtkn.jp>
Date: Thu, 6 Apr 2023 09:46:23 +0900
delete unnecessary files
Diffstat:
6 files changed, 16 insertions(+), 334 deletions(-)
diff --git a/Makefile b/Makefile
@@ -24,12 +24,9 @@ clean:
start.o: start.s
$(AS) $(ASFLAGS) -o start.o start.s
-#boot2_crc.o: boot2/bs2_default_padded_checksummed.S
-# $(AS) $(ASFLAGS) -o boot2_crc.o boot2/bs2_default_padded_checksummed.S
-#boot2/boot2_crc.S: boot2/bs2_default.bin
-# ./bincrc boot2/bs2_default.bin boot2/boot2_crc.S
boot2_crc.o: boot2/boot2_crc.S
$(AS) $(ASFLAGS) -o boot2_crc.o boot2/boot2_crc.S
+
boot2/boot2_crc.S: boot2/boot2.S bincrc
$(AS) $(ASFLAGS) -o boot2/boot2.o boot2/boot2.S
$(OBJCOPY) -O binary boot2/boot2.o boot2/boot2.bin
diff --git a/boot2/boot2.S b/boot2/boot2.S
@@ -75,7 +75,7 @@ wait_sreg:
ldr r1, =((4 << 11) | (2 << 8) | (8 << 2) | (1 << 0))
mov r2, #0xf4
str r1, [r4, r2] // SSI: SPI_CTRLR0
- // re-enable spi
+ // re-enable ssi
mov r1, #1
str r1, [r4, #0x8] // SSI: SSIENR
@@ -90,15 +90,11 @@ wait_sreg:
mov r1, #0x20
str r1, [r4, #0x60] // SSI: DR0
bl wait_ssi
- // I think I need to read rxd-fifo
- // This is not needed because SSI is disabled just after this line.
- //ldr r1, [r4, #0x60]
// set SIP continuous read
// disable ssi
mov r1, #0
str r1, [r4, #0x8] // SSI: SSIENR
- bl assert_rxd_fifo_empty
// the command bit is not documented.
ldr r1, =((0x20 << 24) | (4 << 11) | (0 << 8) | (8 << 2) | (2 << 0))
mov r2, #0xf4
diff --git a/boot2/boot2.S.gen b/boot2/boot2.S.gen
@@ -1,66 +0,0 @@
-.cpu cortex-m0
-.thumb
-
-.equ XIP_BASE, 0x10000000
-.equ XIP_SSI_BASE, 0x18000000
-.equ PPB_BASE, 0xe0000000
-
-.section .text
-
-.global _stage2_boot
-.type _stage2_boot,%function
-.thumb_func
-_stage2_boot:
- push {lr}
-
- ldr r3, =XIP_SSI_BASE
-
- mov r1, #0
- str r1, [r3, #0x8] // SSI_SSIENR
-
- mov r1, #0x4
- str r1, [r3, #0x14] // SSI_BAUDR
-
- mov r1, #0x0
- lsl r1, r1, #21 // SPI_FRF
- mov r2, #31
- lsl r2, r2, #16 // DFS_32
- add r1, r1, r2
- mov r2, #0x0
- lsl r2, r2, #8 // TMOD
- add r1, r1, r2
- str r1, [r3, #0x0] // SSI_CTRLR0
-
- mov r1, #0x03 // read command
- lsl r1, r1, #24
- mov r2, #2 // 8bit instruction
- lsl r2, r2, #8
- add r1, r1, r2
- mov r2, #6 // 24bit address length
- lsl r2, r2, #2
- add r1, r1, r2
- ldr r0, =0xf4
- add r0, r0, r3 // SSI_SPI_CTRLR0
- str r1, [r0, #0x0]
-
- mov r1, #0x0
- str r1, [r3, #0x4] // SSI_CTRLR1_OFFSET
-
- mov r1, #1
- str r1, [r3, #0x8] // SSI_SSIENR_OFFSET
-
- pop {r0}
- cmp r0, #0
- beq vector_into_flash
- bx r0
-vector_into_flash:
- ldr r0, =XIP_BASE
- ldr r2, =0x100
- add r0, r0, r2
- ldr r1, =PPB_BASE
- ldr r2, =0xed08 // M0PLUS_VTOR
- add r1, r1, r2
- str r0, [r1, #0x0]
- ldmia r0, {r0, r1}
- msr msp, r0
- bx r1
diff --git a/boot2/boot2_generic.S b/boot2/boot2_generic.S
@@ -5,62 +5,38 @@
.equ XIP_SSI_BASE, 0x18000000
.equ PPB_BASE, 0xe0000000
-.section .text
-
-.global _stage2_boot
-.type _stage2_boot,%function
.thumb_func
-_stage2_boot:
+boot2:
push {lr}
ldr r3, =XIP_SSI_BASE
mov r1, #0
- str r1, [r3, #0x8] // SSI_SSIENR
-
- mov r1, #0x4
- str r1, [r3, #0x14] // SSI_BAUDR
+ str r1, [r3, #0x8] // SSI: SSIENR
- mov r1, #0x0
- lsl r1, r1, #21 // SPI_FRF
- mov r2, #31
- lsl r2, r2, #16 // DFS_32
- add r1, r1, r2
- mov r2, #0x0
- lsl r2, r2, #8 // TMOD
- add r1, r1, r2
- str r1, [r3, #0x0] // SSI_CTRLR0
+ mov r1, #2
+ str r1, [r3, #0x14] // SSI: BAUDR
+ ldr r1, =((0 << 21) | (31 << 16) | (0 << 8))
+ str r1, [r3, #0x0] // SSI: CTRLR0
- mov r1, #0x03 // read command
- lsl r1, r1, #24
- mov r2, #2 // 8bit instruction
- lsl r2, r2, #8
- add r1, r1, r2
- mov r2, #6 // 24bit address length
- lsl r2, r2, #2
- add r1, r1, r2
ldr r0, =0xf4
- add r0, r0, r3 // SSI_SPI_CTRLR0
- str r1, [r0, #0x0]
+ ldr r1, =((0x03 << 24) | (0x2 << 8) | (6 << 2))
+ str r1, [r3, r0] // SSI: SPI_CTRLR0
- mov r1, #0x0
- str r1, [r3, #0x4] // SSI_CTRLR1_OFFSET
+ mov r1, #0 // NDF = 0
+ str r1, [r3, #0x4] // SSI: CTRLR1
mov r1, #1
- str r1, [r3, #0x8] // SSI_SSIENR_OFFSET
+ str r1, [r3, #0x8] // SSI: SSIENR
pop {r0}
cmp r0, #0
beq vector_into_flash
bx r0
vector_into_flash:
- ldr r0, =XIP_BASE
- ldr r2, =0x100
- add r0, r0, r2
- ldr r1, =PPB_BASE
- ldr r2, =0xed08 // M0PLUS_VTOR
- add r1, r1, r2
- str r0, [r1, #0x0]
+ ldr r0, =(XIP_BASE + 0x100)
+ ldr r1, =(PPB_BASE + 0xed08)
+ str r0, [r1, #0x0] // M0PLUS: VTOR
ldmia r0, {r0, r1}
msr msp, r0
bx r1
diff --git a/boot2/boot2_w25q.S b/boot2/boot2_w25q.S
@@ -1,198 +0,0 @@
-.equ XIP_SSI_BASE, 0x18000000
-.equ PADS_QSPI_BASE, 0x40020000
-.equ PPB_BASE, 0xe0000000
-.equ XIP_BASE, 0x10000000
-
-.syntax unified
-.cpu cortex-m0plus
-.thumb
-
-.section .text
-
-.global _stage2_boot
-.type _stage2_boot,%function
-.thumb_func
-_stage2_boot:
- push {lr}
-
- ldr r3, =PADS_QSPI_BASE
- movs r0, #(2 << 4 | 1)
- str r0, [r3, #0x4]
- ldr r0, [r3, #0x8]
- movs r1, #2
- bics r0, r1
- str r0, [r3, #0x8]
- str r0, [r3, #0xc]
- str r0, [r3, #0x10]
- str r0, [r3, #0x14]
-
- ldr r3, =XIP_SSI_BASE
-
- // Disable SSI to allow further config
- movs r1, #0
- str r1, [r3, #0x8] // SSI: SSIENR
-
- // Set baud rate
- movs r1, #4
- str r1, [r3, #0x14] // SSI: BAUDR
-
- // Set 1-cycle sample delay. If 4 == 2 then this means,
- // if the flash launches data on SCLK posedge, we capture it at the time that
- // the next SCLK posedge is launched. This is shortly before that posedge
- // arrives at the flash, so data hold time should be ok. For
- // 4 > 2 this pretty much has no effect.
-
- movs r1, #1
- movs r2, #0xf0
- str r1, [r3, r2]
-
-
-// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
-// (i.e. turn WPn and HOLDn into IO2/IO3)
-program_sregs:
- ldr r1, =((7 << 16) | (0 << 8))
- str r1, [r3, #0] // SSI: CTRLR0
-
- // Enable SSI and select slave 0
- movs r1, #1
- str r1, [r3, #0x8] // SSI: SSIENR
-
- // Check whether SR needs updating
- movs r0, #0x35
- bl read_flash_sreg
- movs r2, #0x02
- cmp r0, r2
- beq skip_sreg_programming
-
- // Send write enable command
- movs r1, #0x06
- str r1, [r3, #0x60]
-
- // Poll for completion and discard RX
- bl wait_ssi_ready
- ldr r1, [r3, #0x60]
-
- // Send status write command followed by data bytes
- movs r1, #0x01
- str r1, [r3, #0x60]
- movs r0, #0
- str r0, [r3, #0x60]
- str r2, [r3, #0x60]
-
- bl wait_ssi_ready
- ldr r1, [r3, #0x60]
- ldr r1, [r3, #0x60]
- ldr r1, [r3, #0x60]
-
- // Poll status register for write completion
-1:
- movs r0, #0x05
- bl read_flash_sreg
- movs r1, #1
- tst r0, r1
- bne 1b
-
-skip_sreg_programming:
-
- // Disable SSI again so that it can be reconfigured
- movs r1, #0
- str r1, [r3, #0x8]
-
-// Currently the flash expects an 8 bit serial command prefix on every
-// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
-// command, with mode bits set such that the flash will not expect a serial
-// command prefix on *subsequent* transfers. We don't care about the results
-// of the read, the important part is the mode bits.
-
-dummy_read:
- ldr r1, =((2 << 21) | (31 << 16) | (3 << 8))
- str r1, [r3, #0x0]
-
- movs r1, #0x0 // NDF=0 (single 32b read)
- str r1, [r3, #0x4]
-
- ldr r1, =((8 << 2) | (4 << 11) | (2 << 8) | (1 << 0))
- ldr r0, =(XIP_SSI_BASE + 0xf4) // SPI_CTRL0 Register
- str r1, [r0]
-
- movs r1, #1 // Re-enable SSI
- str r1, [r3, #0x8]
-
- movs r1, #0xeb
- str r1, [r3, #0x60] // Push SPI command into TX FIFO
- movs r1, #0xa0 // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
- str r1, [r3, #0x60] // Push Address into TX FIFO - this will trigger the transaction
-
- // Poll for completion
- bl wait_ssi_ready
-
-// The flash is in a state where we can blast addresses in parallel, and get
-// parallel data back. Now configure the SSI to translate XIP bus accesses
-// into QSPI transfers of this form.
-
- movs r1, #0
- str r1, [r3, #0x8] // Disable SSI (and clear FIFO) to allow further config
-
-// Note that the INST_L field is used to select what XIP data gets pushed into
-// the TX FIFO:
-// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
-// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
-configure_ssi:
- ldr r1, =((0xa0 << 24) | (8 << 2) | (4 << 11) | (0 << 8) | (2 << 0))
- ldr r0, =(XIP_SSI_BASE + 0xf4)
- str r1, [r0]
-
- movs r1, #1
- str r1, [r3, #0x8] // Re-enable SSI
-
-// Bus accesses to the XIP window will now be transparently serviced by the
-// external flash on cache miss. We are ready to run code from flash.
-
-// Pull in standard exit routine
-check_return:
- pop {r0}
- cmp r0, #0
- beq vector_into_flash
- bx r0
-vector_into_flash:
- ldr r0, =(XIP_BASE + 0x100)
- ldr r1, =(PPB_BASE + 0xed08)
- str r0, [r1]
- ldmia r0, {r0, r1}
- msr msp, r0
- bx r1
-
-wait_ssi_ready:
- push {r0, r1, lr}
-
- // Command is complete when there is nothing left to send
- // (TX FIFO empty) and SSI is no longer busy (CSn deasserted)
-1:
- ldr r1, [r3, #0x28]
- movs r0, #4
- tst r1, r0
- beq 1b
- movs r0, #1
- tst r1, r0
- bne 1b
-
- pop {r0, r1, pc}
-
-read_flash_sreg:
- push {r1, lr}
- str r0, [r3, #0x60]
- // Dummy byte:
- str r0, [r3, #0x60]
-
- bl wait_ssi_ready
- // Discard first byte and combine the next two
- ldr r0, [r3, #0x60]
- ldr r0, [r3, #0x60]
-
- pop {r1, pc}
-
-.global literals
-literals:
-.ltorg
-
-.end
diff --git a/boot2/bs2_default_padded_checksummed.S b/boot2/bs2_default_padded_checksummed.S
@@ -1,23 +0,0 @@
-// Padded and checksummed version of: /home/kenji/code/pico/pico-sdk/build/src/rp2_common/boot_stage2/bs2_default.bin
-
-.cpu cortex-m0plus
-.thumb
-
-.section .boot2, "ax"
-
-.byte 0x00, 0xb5, 0x32, 0x4b, 0x21, 0x20, 0x58, 0x60, 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60
-.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2e, 0x4b, 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61
-.byte 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2b, 0x49, 0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20
-.byte 0x00, 0xf0, 0x44, 0xf8, 0x02, 0x22, 0x90, 0x42, 0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0
-.byte 0x34, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66, 0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0
-.byte 0x2c, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e, 0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21
-.byte 0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60, 0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60
-.byte 0x1a, 0x49, 0x1b, 0x48, 0x01, 0x60, 0x01, 0x21, 0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21
-.byte 0x19, 0x66, 0x00, 0xf0, 0x12, 0xf8, 0x00, 0x21, 0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60
-.byte 0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28, 0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49
-.byte 0x08, 0x60, 0x03, 0xc8, 0x80, 0xf3, 0x08, 0x88, 0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20
-.byte 0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42, 0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66
-.byte 0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e, 0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40
-.byte 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00, 0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00
-.byte 0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0, 0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0
-.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a
