commit dc97c51612c9f10fbd30710e2001ecb25ad40556
parent 8339cebb8f88c8d33f83a2f8baa423691716ffe2
Author: Matsuda Kenji <info@mtkn.jp>
Date: Thu, 6 Apr 2023 09:12:31 +0900
rxd-fifo gets empty when SSI is disabled
Diffstat:
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/boot2/boot2.S b/boot2/boot2.S
@@ -91,21 +91,14 @@ wait_sreg:
str r1, [r4, #0x60] // SSI: DR0
bl wait_ssi
// I think I need to read rxd-fifo
- ldr r1, [r4, #0x60]
-/*
-// this loop is for test if the rxd-fifo is empty.
-// the fifo is not empty without the ldr instruction above.
-loop:
- ldr r1, [r4, #0x28] // SSI: SR
- mov r2, #8 // RFNE
- tst r1, r2
- bne loop
-*/
+ // This is not needed because SSI is disabled just after this line.
+ //ldr r1, [r4, #0x60]
// set SIP continuous read
// disable ssi
mov r1, #0
str r1, [r4, #0x8] // SSI: SSIENR
+ bl assert_rxd_fifo_empty
// the command bit is not documented.
ldr r1, =((0x20 << 24) | (4 << 11) | (0 << 8) | (8 << 2) | (2 << 0))
mov r2, #0xf4
@@ -128,6 +121,14 @@ vector_into_flash:
msr msp, r0
bx r1
+assert_rxd_fifo_empty:
+ push {r1, r2, lr}
+ ldr r1, [r4, #0x28] // SSI: SR
+ mov r2, #8 // RFNE
+ tst r1, r2
+ bne assert_rxd_fifo_empty
+ pop {r1, r2, pc}
+
wait_ssi:
// asumes that r4 is XIP_SSI_BASE
ldr r1, [r4, #0x28] // SSI: SR
