commit 202988ba1987f7f3707fa9f57543e547bacc288f
parent dcbb7254695fb1161257f98cf94a9222d290f3e0
Author: Matsuda Kenji <info@mtkn.jp>
Date: Mon, 1 May 2023 10:35:37 +0900
add putchar and getchar,
change order of uart0 setup
Diffstat:
| M | ex2/main.s | | | 59 | ++++++++++++++++++++++++++++++++++++++++++++++++++++++----- |
1 file changed, 54 insertions(+), 5 deletions(-)
diff --git a/ex2/main.s b/ex2/main.s
@@ -85,23 +85,72 @@ wait_vco:
ldr r1, atomic_set
add r1, r1, #0x30
str r0, [r3, r1] // UART: UARTCR
- // enable FIFO and set format
- ldr r0, =(3 << 5 | 1 << 4) // 8bit WLEN | FEN
- str r0, [r3, #0x2c] // UART: UARTLCR_H
// set baudrate 115200
// BDRI = 72, BDRF = 0.157 (10 / 64)
mov r0, #72
str r0, [r3, #0x24] // UART: UARTIBRD
mov r0, #10
str r0, [r3, #0x28] // UART: UARTFBRD
+ // enable FIFO and set format
+ ldr r0, =(3 << 5 | 1 << 4) // WLEN = 8
+ str r0, [r3, #0x2c] // UART: UARTLCR_H
loop:
- bl bled0
- bl bled1
+ bl getchar
+ bl putchar
b loop
// functions
+ // print r0 in hex
+printh:
+ push {r4, r5, r6, r7, lr}
+ mov r4, r0
+ mov r5, #28
+ mov r6, #0xf
+ mov r7, #10
+printh_loop:
+ mov r0, r4
+ lsr r0, r0, r5
+ and r0, r0, r6
+ sub r1, r0, r7
+ blt digi
+ add r0, r0, #('a' - 10)
+ b alpha
+digi:
+ add r0, r0, #'0'
+alpha:
+ bl putchar
+ sub r5, r5, #4
+ bge printh_loop
+ pop {r4, r5, r6, r7, pc}
+
+putchar:
+ ldr r3, uart0_base
+ mov r1, #1
+ lsl r1, r1, #5 // TXFF
+txff:
+ ldr r2, [r3, #0x18] // UART: UARTFR
+ tst r1, r2
+ bne txff
+ mov r1, #0xff
+ and r0, r0, r1
+ str r0, [r3, #0] // UART: UARTDR
+ bx lr
+
+getchar:
+ ldr r3, uart0_base
+ mov r1, #1
+ lsl r1, r1, #4 // RXFE
+rxfe:
+ ldr r2, [r3, #0x18] // UART: UARTFR
+ tst r1, r2
+ bne rxfe
+ ldr r0, [r3, #0] // UART: UARTDR
+ mov r1, #0xff
+ and r0, r0, r1
+ bx lr
+
// The following functions make no side effects and
// can be used anywhare without pushing and popping
// registers.
