commit fa41209db53d0ade358e45436a9e3234e3231d0d
parent cf14664f38068b6d78b9c858fdb9da75c8c1ee0f
Author: Matsuda Kenji <info@mtkn.jp>
Date: Tue, 4 Apr 2023 09:33:35 +0900
modify boot2
Diffstat:
3 files changed, 34 insertions(+), 77 deletions(-)
diff --git a/Makefile b/Makefile
@@ -30,8 +30,8 @@ start.o: start.s
# ./bincrc boot2/bs2_default.bin boot2/boot2_crc.S
boot2_crc.o: boot2/boot2_crc.S
$(AS) $(ASFLAGS) -o boot2_crc.o boot2/boot2_crc.S
-boot2/boot2_crc.S: boot2/boot2_w25q.S bincrc
- $(AS) $(ASFLAGS) -o boot2/boot2.o boot2/boot2_w25q.S
+boot2/boot2_crc.S: boot2/boot2.S bincrc
+ $(AS) $(ASFLAGS) -o boot2/boot2.o boot2/boot2.S
$(OBJCOPY) -O binary boot2/boot2.o boot2/boot2.bin
./bincrc boot2/boot2.bin boot2/boot2_crc.S
diff --git a/boot2/boot2.S b/boot2/boot2.S
@@ -10,18 +10,8 @@ boot2:
push {lr}
ldr r0, =PADS_QSPI_BASE
- mov r1, #2 // 8mA
- lsr r1, r1, #4 // SCLK_DRIVE
- add r1, r1, #1 // slew fast
+ ldr r1, =(2 << 4 | 1) // 8mA, slew fast
str r1, [r0, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
- // clear schmitt bit
- ldr r1, [r0, #0x8] // PADS_QSPI: GPIO_QSPI_SD0
- mov r2, #0x2 // schmitt trigger
- bic r1, r2
- str r1, [r3, #0x8] // PADS_QSPI: GPIO_QSPI_SD0
- str r1, [r3, #0xc] // PADS_QSPI: GPIO_QSPI_SD1
- str r1, [r3, #0x10] // PADS_QSPI: GPIO_QSPI_SD2
- str r1, [r3, #0x14] // PADS_QSPI: GPIO_QSPI_SD3
ldr r0, =XIP_SSI_BASE
@@ -30,20 +20,16 @@ boot2:
str r1, [r0, #0x8] // SSI: SSIENR
//set divider
- mov r1, #0x4
+ ldr r1, =0x2 // This is 2 in sdk
str r1, [r0, #0x14] // SSI: BAUDR
// set 1-cycle sample delay.
mov r1, #1
- mov r2, #0xa0
+ mov r2, #0xf0
str r1, [r0, r2] // SSI: RX_SAMPLE_DLY
// setup sregs
- mov r1, #0x7 // 8bit data frame size
- lsl r1, r1, #16 // DFS_32
- mov r2, #0 // transmit and recieve
- lsl r2, r2, #8 // TMOD
- add r1, r1, r2
+ ldr r1, =((7 << 16) | (0 << 8)) // 8bit data frame size, tx and rx
str r1, [r0, #0] // SSI: CTRLR0
// enable ssi
@@ -60,51 +46,40 @@ boot2:
// set sreg
mov r1, #0x31 // write status register-2
str r1, [r0, #0x60] // SSI: DR0
- mov r1, #0 // is this needed?
- str r1, [r0, #0x60] // SSI: DR0 is this needed?
mov r1, #0x2 // quad enable
str r1, [r0, #0x60] // SSI: DR0
bl wait_ssi
ldr r1, [r0, #0x60] // SSI: DR0
ldr r1, [r0, #0x60] // SSI: DR0
+
+wait_sreg:
+ mov r1, #0x5 // read status register-1
+ // maybe the first str represents the command and
+ // does the second one the address.
+ str r1, [r0, #0x60] // SSI: DR0
+ str r1, [r0, #0x60] // SSI: DR0
+ bl wait_ssi
+ ldr r0, =XIP_SSI_BASE
+ ldr r1, [r0, #0x60] // SSI: DR0
ldr r1, [r0, #0x60] // SSI: DR0
-wait_sreg_lock:
- mov r0, #0x35 // read status register-2
- bl read_sreg
- mov r1, #1
- tst r0, r1
- bne wait_sreg_lock
+ mov r2, #1 // BUSY flag
+ tst r1, r2
+ bne wait_sreg
// disable ssi again
- ldr r0, =XIP_SSI_BASE
mov r1, #0
str r1, [r0, #0x8] // SSI: SSIENR
// set up quad spi
- mov r1, #2 // quad spi
- lsl r1, r1, #21 // SPI_FRF
- mov r2, #31 // 32bit data frame
- lsl r2, r2, #16 // DFS_32
- add r1, r1, r2
- mov r2, #3 // eeprom mode ???
- lsl r2, r2, #8 // TMOD
- add r1, r1, r2
+ ldr r1, =((2 << 21) | (31 << 16)| (0 << 8)) // tmod is 3 in sdk
str r1, [r0, #0] // SSI: CTRLR0
mov r1, #0 // NDF = 0
str r1, [r0, #0x4] // SSI: CTRLR1
// setup xip
- mov r1, #4 // 4 dummy clocks
- lsl r1, r1, #11 // WAIT_CYCLES
- mov r2, #2 // 8bit instruction
- lsl r2, r2, #8 // INST_L
- add r1, r1, r2
- mov r2, #8 // address + mode bits
- lsl r2, r2, #2 // ADDR_L
- add r1, r1, r2
- add r1, r1, #1 // TRANS_TYPE: command: standard, address: quad
+ ldr r1, =((4 << 11) | (2 << 8) | (8 << 2) | (1 << 0))
mov r2, #0xf4
str r1, [r0, r2] // SSI: SPI_CTRLR0
@@ -114,28 +89,22 @@ wait_sreg_lock:
mov r1, #0xeb // fast read quad i/o
str r1, [r0, #0x60] // SSI: DR0
- mov r1, #0xa0 // 0xa0 is for w25q80bv. 0xf0 is for w25q16j??
+ // continuous read is not documented in w25q16j datasheet...
+ // it says mode bits shoud be Fxh (x: don't care)...
+ // in w2580bv datasheet, these bits are said to be 0bxx10xxxx.
+ // why w25q16j lacks the description?
+ mov r1, #0x20
str r1, [r0, #0x60] // SSI: DR0
bl wait_ssi
// I think I need to read rxd-fifo
+ // ldr r1, [r0, #0x60]
// disable spi
mov r1, #0
str r1, [r0, #0x8] // SSI: SSIENR
- mov r1, #0xa0
- lsl r1, r1, #24
- mov r2, #4 // 4 dummy clocks
- lsl r2, r2, #11 // WAIT_CYCLES
- add r1, r1, r2
- mov r2, #0 // no instruction
- lsl r2, r2, #8 // INST_L
- add r1, r1, r2
- mov r2, #8 // 24bit address + 8bit mode
- lsl r2, r2, #2 // ADDR_L
- add r1, r1, r2
- add r1, r1, #2 // TRANS_TYPE: both in quad
-
+ // the command bit is not documented.
+ ldr r1, =((0x20 << 24) | (4 << 11) | (0 << 8) | (8 << 2) | (2 << 0))
mov r2, #0xf4
str r1, [r0, r2] // SSI: SPI_CTRLR0
@@ -148,12 +117,9 @@ wait_sreg_lock:
beq vector_into_flash
bx r0
vector_into_flash:
- ldr r0, =XIP_BASE
- ldr r1, =0x100
- add r0, r0, r1
- ldr r1, =PPB_BASE
- ldr r2, =0xed08
- str r0, [r1, r2] // M0PLUS: VTOR
+ ldr r0, =(XIP_BASE + 0x100)
+ ldr r1, =(PPB_BASE + 0xed08)
+ str r0, [r1, #0] // M0PLUS: VTOR
ldmia r0, {r0, r1}
msr msp, r0
bx r1
@@ -168,13 +134,4 @@ wait_ssi:
tst r1, r2
bne wait_ssi
bx lr
-
-read_sreg:
- // I don't understand why dummy byte is needed
- push {lr}
- ldr r1, =XIP_SSI_BASE
- str r0, [r1, #0x60] // SSI: DR0
- bl wait_ssi
- ldr r1, =XIP_SSI_BASE
- ldr r0, [r1, #0x60] // SSI: DR0
- pop {pc}
+literals:
diff --git a/boot2/boot2_w25q.S b/boot2/boot2_w25q.S
@@ -33,7 +33,7 @@ _stage2_boot:
str r1, [r3, #0x8] // SSI: SSIENR
// Set baud rate
- movs r1, #2
+ movs r1, #4
str r1, [r3, #0x14] // SSI: BAUDR
// Set 1-cycle sample delay. If 4 == 2 then this means,
