commit da3237e59d6844564cea59e62c633f1b67c69448
parent b531ac7c4ac8d9a9df07600520ef130a3284ace4
Author: Matsuda Kenji <info@mtkn.jp>
Date: Fri, 29 Aug 2025 20:28:00 +0900
use more c
Diffstat:
2 files changed, 72 insertions(+), 45 deletions(-)
diff --git a/ex4_shell/main.c b/ex4_shell/main.c
@@ -5,11 +5,19 @@ typedef enum reset_bit {
} reset_bit;
void unreset(reset_bit);
+void init_xosc(void);
+void init_pll(void);
+void enable_clock_peri(void);
+void set_system_clock_to_pll_sys(void);
void mains(void);
void
main(void)
{
+ enable_clock_peri();
unreset(RESET_IOBANK0|RESET_PLL_SYS|RESET_UART0);
+ init_xosc();
+ init_pll();
+ set_system_clock_to_pll_sys();
mains();
}
diff --git a/ex4_shell/start.s b/ex4_shell/start.s
@@ -58,49 +58,11 @@ loop:
wfe
b loop
- // void unreset(reset_bit subsystems);
- // unreset unresets subsystems.
- // subsystems is bitwise or.
- .global unreset
-unreset:
- // unreset gpio, pll_sys, uart0
- ldr r3, resets_base
- ldr r1, atomic_clr
- str r0, [r3, r1] // RESETS: RESET
- mov r1, #1
- lsl r1, #22
- bic r0, r1 // uart stays in reset state until clock_peri is enabled
-unreset_chk:
- ldr r1, [r3, #0x8] // RESETS: RESET_DONE
- bic r0, r1
- bne unreset_chk
- bx lr
-
- .global mains
-mains:
- push {lr}
-
- // set gpio functions
- ldr r3, io_bank0_base
- // set pins 0 and 1 for uart
- mov r0, #2 // uart0
- mov r1, #0x4
- str r0, [r3, r1] // IO_BANK0: GPIO0_CTRL
- mov r1, #0xc
- str r0, [r3, r1] // IO_BANK0: GPIO1_CTRL
- // set pins 24 and 25 to SIO for led blink.
- mov r0, #5 // sio
- mov r1, #0xc4
- str r0, [r3, r1] // IO_BANK0: GPIO24_CTRL
- mov r1, #0xcc
- str r0, [r3, r1] // IO_BANK0: GPIO24_CTRL
-
- // enable sio output
- ldr r3, sio_base
- mov r0, #0b11
- lsl r0, r0, #24
- str r0, [r3, #0x24] // SIO: GPIO_OE
-
+ // void init_clock(void);
+ // init_clock initialize xosc and set it as the system clock
+ // clock freq is 133MHz.
+ .global init_xosc
+init_xosc:
// setup xosc
ldr r3, xosc_base
mov r0, #47 // start up delay for 12MHz rosc (xosc?)
@@ -111,8 +73,12 @@ wait_xosc:
ldr r0, [r3, #0x4] // XOSC: STATUS
lsr r0, r0, #31 // STABLE bit
beq wait_xosc
+ bx lr
- // setup pll_sys 133MHz
+ // void init_pll(void);
+ // init_pll setups pll_sys in 133MHz.
+ .global init_pll
+init_pll:
ldr r3, pll_sys_base
// set feedback divider
mov r0, #133
@@ -133,15 +99,67 @@ wait_vco:
// power on post divider
mov r0, #8 // POSTDIVPD
str r0, [r3, r1] // PLL: PWR
+ bx lr
+ // void set_system_clock_to_pll_sys(void);
+ // set_system_clock_to_pll_sys sets system clock to pll_sys
+ .global set_system_clock_to_pll_sys
+set_system_clock_to_pll_sys:
// set system clock clksrc_pll_sys
ldr r3, clocks_base
ldr r0, =(0x0 << 5 | 0x1)
str r0, [r3, #0x3c] // CLOCKS: CLK_SYS_CTRL
- // enable clk_peri
+ bx lr
+
+ // void enable_clock_peri(void);
+ // enable_clock_peri enables clk_peri and set it to clk_sys
+ .global enable_clock_peri
+enable_clock_peri:
mov r0, #1
lsl r0, r0, #11
+ ldr r3, clocks_base
str r0, [r3, #0x48] // CLOCKS: CLK_PERI_CTRL
+ bx lr
+
+ // void unreset(reset_bit subsystems);
+ // unreset unresets subsystems.
+ // subsystems is bitwise or.
+ // To unreset uart, clk_peri must be enabled beforehand.
+ .global unreset
+unreset:
+ ldr r3, resets_base
+ ldr r1, atomic_clr
+ str r0, [r3, r1] // RESETS: RESET
+unreset_chk:
+ ldr r1, [r3, #0x8] // RESETS: RESET_DONE
+ bic r0, r1
+ bne unreset_chk
+ bx lr
+
+ .global mains
+mains:
+ push {lr}
+
+ // set gpio functions
+ ldr r3, io_bank0_base
+ // set pins 0 and 1 for uart
+ mov r0, #2 // uart0
+ mov r1, #0x4
+ str r0, [r3, r1] // IO_BANK0: GPIO0_CTRL
+ mov r1, #0xc
+ str r0, [r3, r1] // IO_BANK0: GPIO1_CTRL
+ // set pins 24 and 25 to SIO for led blink.
+ mov r0, #5 // sio
+ mov r1, #0xc4
+ str r0, [r3, r1] // IO_BANK0: GPIO24_CTRL
+ mov r1, #0xcc
+ str r0, [r3, r1] // IO_BANK0: GPIO24_CTRL
+
+ // enable sio output
+ ldr r3, sio_base
+ mov r0, #0b11
+ lsl r0, r0, #24
+ str r0, [r3, #0x24] // SIO: GPIO_OE
// setup uart0
ldr r3, uart0_base
@@ -257,6 +275,7 @@ pled1:
pop {r0, r1, r2, r3, r4, r5, r6, pc}
// bled0 blinks the led on the pin 24 once.
+ .global bled0
bled0:
push {r0, r1, r2, r3, lr}
mov r0, #1
