commit c0a0613103de96559737c5f07b8d9c3a67d86168
parent 1694d98d764b5456e9596cc5fe14000e0084430d
Author: Matsuda Kenji <info@mtkn.jp>
Date: Wed, 12 Apr 2023 08:06:29 +0900
refactor boot2
Diffstat:
2 files changed, 28 insertions(+), 25 deletions(-)
diff --git a/boot2/boot2.s b/boot2/boot2.s
@@ -1,12 +1,14 @@
.cpu cortex-m0plus
.thumb
-
+ .global boot2
+ .thumb_func
boot2:
push {r4, lr}
+ // setup QSPI pad
ldr r4, pads_qspi_base
- ldr r1, =(2 << 4 | 1) // 8mA, slew fast
+ ldr r1, =(0 << 4 | 0 << 1 | 1) // 2mA, schmitt off, slew fast
str r1, [r4, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
// r4 should not be changed from this point on
@@ -17,15 +19,17 @@ boot2:
mov r1, #0
str r1, [r4, #0x8] // SSI: SSIENR
//set divider
- mov r1, #0x2 // This is 2 in sdk
+ mov r1, #0x2
str r1, [r4, #0x14] // SSI: BAUDR
// set 1-cycle sample delay.
mov r1, #1
mov r2, #0xf0
str r1, [r4, r2] // SSI: RX_SAMPLE_DLY
- // setup sregs
- ldr r1, =((7 << 16) | (0 << 8)) // 8bit data frame size, tx and rx
+ // setup SSI
+ ldr r1, =(7 << 16 | 3 << 8) // 8bit data frame size, eeprom
str r1, [r4, #0] // SSI: CTRLR0
+ mov r1, #0 // NDF = 0
+ str r1, [r4, #0x4] // SSI: CTRLR1
// enable SSI
mov r1, #1
str r1, [r4, #0x8] // SSI: SSIENR
@@ -36,7 +40,7 @@ boot2:
str r1, [r4, #0x60] // SSI: DR0
bl wait_ssi
ldr r1, [r4, #0x60] // SSI: DR0
- // set sreg
+ // enable QSPI
mov r1, #0x31 // write status register-2
str r1, [r4, #0x60] // SSI: DR0
mov r1, #0x2 // quad enable
@@ -47,13 +51,17 @@ boot2:
wait_sreg:
mov r1, #0x5 // read status register-1
- // maybe the first str represents the command
- // while does the second one the address.
- str r1, [r4, #0x60] // SSI: DR0
+ // This str is required twice if TMOD = 0.
+ // In this case, /CS signal is set to high just
+ // after the first str instruction and the flash
+ // doesn't shift out the status register.
+ // On the other hand, If TMOD = 3 (eeprom),
+ // then the /CS is kept to low until NDF + 1
+ // data frames are captured.
+ // Shiran Kedo.
str r1, [r4, #0x60] // SSI: DR0
bl wait_ssi
ldr r1, [r4, #0x60] // SSI: DR0
- ldr r1, [r4, #0x60] // SSI: DR0
mov r2, #1 // BUSY flag
tst r1, r2
bne wait_sreg
@@ -62,13 +70,15 @@ wait_sreg:
// disable SSI
mov r1, #0
str r1, [r4, #0x8] // SSI: SSIENR
- // set up quad spi
- ldr r1, =((2 << 21) | (31 << 16)| (0 << 8)) // tmod is 3 in sdk
+ // set up QSPI
+ // DFS is said to be the number of clocks of a data frame - 1.
+ // But in QSPI mode, a frame is 32 bits and is transfered in 8 clocks.
+ // However, if DFS is set to 7, It doesn't work.
+ // Maybe this is a bug of the documentation.
+ ldr r1, =(2 << 21 | 31 << 16 | 3 << 8) // quad, 32bit data frame, eeprom
str r1, [r4, #0] // SSI: CTRLR0
- mov r1, #0 // NDF = 0
- str r1, [r4, #0x4] // SSI: CTRLR1
// setup xip
- ldr r1, =((4 << 11) | (2 << 8) | (8 << 2) | (1 << 0))
+ ldr r1, =(4 << 11 | 2 << 8 | 8 << 2 | 1 << 0)
mov r2, #0xf4
str r1, [r4, r2] // SSI: SPI_CTRLR0
// re-enable SSI
@@ -92,7 +102,7 @@ wait_sreg:
mov r1, #0
str r1, [r4, #0x8] // SSI: SSIENR
// the command bit is not documented.
- ldr r1, =((0x20 << 24) | (4 << 11) | (0 << 8) | (8 << 2) | (2 << 0))
+ ldr r1, =(0x20 << 24 | 4 << 11 | 0 << 8 | 8 << 2 | 2 << 0)
mov r2, #0xf4
str r1, [r4, r2] // SSI: SPI_CTRLR0
// re-enable SSI
@@ -125,14 +135,6 @@ initial_boot:
mov sp, r0
bx r1
-assert_rxd_fifo_empty:
- push {r1, r2, lr}
- ldr r1, [r4, #0x28] // SSI: SR
- mov r2, #8 // RFNE
- tst r1, r2
- bne assert_rxd_fifo_empty
- pop {r1, r2, pc}
-
wait_ssi:
// asumes that r4 is xip_ssi_base
ldr r1, [r4, #0x28] // SSI: SR
@@ -144,6 +146,7 @@ wait_ssi:
bne wait_ssi
bx lr
+ .align 2
boot2_end:
.word 0x10000000 + 0x100
xip_ssi_base:
diff --git a/main.c b/main.c
@@ -6,6 +6,6 @@ main(void)
{
init();
while(1) {
- ;
+ led_p2();
}
}
