commit a0c6afd9d8c55169f254d251a6d993c42aaa3890
parent af5e48178c47f131cd874c7c8e8b168c708b299c
Author: Matsuda Kenji <info@mtkn.jp>
Date: Sat, 22 Apr 2023 09:46:49 +0900
work
Diffstat:
4 files changed, 28 insertions(+), 310 deletions(-)
diff --git a/ex1/Makefile b/ex1/Makefile
@@ -10,7 +10,7 @@ ASFLAGS = $(MCPU)
CFLAGS = $(MCPU) -ffreestanding -nostartfiles -O0 -fpic -mthumb -c
LDFLAGS = --no-relax -nostdlib
-all: led.uf2
+all: tools led.uf2
clean:
rm -f *.o *.elf *.uf2 *.bin
diff --git a/ex1/boot2.s b/ex1/boot2.s
@@ -2,16 +2,14 @@
.thumb
.section .boot2
- .global setup_xip
.thumb_func
setup_xip:
- push {r4, lr}
-
+/*
// setup QSPI pad
ldr r4, pads_qspi_base
ldr r1, =(0 << 4 | 0 << 1 | 1) // 2mA, schmitt off, slew fast
str r1, [r4, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
-
+*/
ldr r4, rom_base
ldrh r0, [r4, #0x14] // rom_func_table
@@ -20,29 +18,7 @@ setup_xip:
blx r2
blx r0
- // this code should be rewritten using dma.
- ldr r2, boot2_end
- ldr r3, sram_base
- ldr r0, etext
- sub r0, r0, r3
- add r0, #3
- lsr r0, #2
-sram_cpy:
- ldr r1, [r2, #0]
- str r1, [r3, #0]
- add r2, r2, #0x4
- add r3, r3, #0x4
- sub r0, r0, #0x1
- bne sram_cpy
-
- // exit from boot2
- pop {r4}
- pop {r0}
- cmp r0, #0
- beq initial_boot
- bx r0
-initial_boot:
- ldr r0, sram_base
+ ldr r0, boot2_end
ldr r1, m0plus_vtor
str r0, [r1, #0] // M0PLUS: VTOR
ldr r1, [r0, #4] // entry point
@@ -55,14 +31,10 @@ rom_base:
.word 0x00000000
boot2_end:
.word 0x10000000 + 0x100
-sram_base:
- .word 0x20000000
pads_qspi_base:
.word 0x40020000
m0plus_vtor:
.word 0xe0000000 + 0xed08
-etext:
- .word _etext
literals:
.ltorg
diff --git a/ex1/main.s b/ex1/main.s
@@ -7,300 +7,47 @@ vectors:
.word (reset+1) // entry point
.section .text
- .thumb_func
reset:
- bl main
-hang:
- b hang
-
- .global init
- .thumb_func
-init:
- push {r4, r5, lr}
- // unreset gpio and pll_sys and uart0
- mov r1, #1
- lsl r0, r1, #5 // io_bank0
- lsl r1, r1, #12 // pll_sys
- add r0, r0, r1
- lsl r1, r1, #10 // uart0
- add r0, r0, r1
- bl unreset
- bl wait_unreset
-
- // set gpio functions
- ldr r0, io_bank0_base
- mov r1, #2 // uart0
- mov r2, #5 // sio
- add r0, r0, #0x4 // io_bank0_gpio0_ctrl
- str r1, [r0, #0] // uart0
- add r0, r0, #0x8 // #0xc io_bank0_gpio1_ctrl
- str r1, [r0, #0] // uart0
- add r0, r0, #0xa8 // #0xb4 io_bank0_gpio22_ctrl
- str r2, [r0, #0] // sio
- add r0, r0, #0x10 // #0xc4 io_bank0_gpio24_ctrl
- str r2, [r0, #0] // sio
-
- // enable gpio output
- ldr r0, sio_base
- mov r1, #5
- lsl r1, r1, #22 // gpio22 and gpio24
- str r1, [r0, #0x24]
-
- // enable xosc
- ldr r0, xosc_base
- mov r1, #0xf
- lsl r1, r1, #8
- add r1, r1, #0xab
- lsl r1, r1, #8
- add r1, r1, #0xaa
- lsl r1, r1, #4
- str r1, [r0, #0] // XOSC_CTRL
-
- // set xosc delay
- mov r1, #47
- str r1, [r0, #0xc] // XOSC_STARTUP
-
- // wait for xosc startup
-xosc_stable:
- ldr r1, [r0, #0x4] // XOSC_STATUS
- lsr r1, r1, #31
- beq xosc_stable
-
- // set pll feedback divider
- ldr r0, pll_sys_base
- mov r1, #125
- str r1, [r0, #0x8] // PLL_FBDIV_INT
-
- // power on pll
- ldr r1, atomic_clr
- add r0, r0, r1
- mov r1, #33 // VCOPD | PD
- str r1, [r0, #0x4] // PLL_PWR
-
- // wait for pll locking
- ldr r0, pll_sys_base
-pll_lock:
- ldr r1, [r0, #0] // PLL_CS
- lsr r1, r1, #31
- beq pll_lock
-
- // set post dividers
- ldr r0, pll_sys_base
- ldr r1, atomic_clr
- add r0, r0, r1
- mov r1, #3
- lsl r1, r1, #4
- add r1, r1, #4
- lsl r1, r1, #12
- str r1, [r0, #0xc] // PLL_PRIM
-
- // turn on post dividers
- ldr r0, pll_sys_base
+ // unreset gpio
+ mov r0, #1
+ lsl r0, r0, #5 // io_bank0
+ ldr r3, resets_base
ldr r1, atomic_clr
- add r0, r0, r1
- mov r1, #8
- str r1, [r0, #0x4] // PLL_PWR
-
- // set sys clock to pll_sys
- ldr r0, clocks_base
- mov r1, #1
- str r1, [r0, #0x3c] // CLOCKS_CLK_SYS_CTRL
- // enable clk_peri
- lsl r1, r1, #11
- str r1, [r0, #0x48]
-
- // enable clk_peri
- ldr r0, clocks_base
- mov r1, #1
- lsl r1, r1, #11
- str r1, [r0, #0x48] // CLOCKS_CLK_PERI_CTRL
-
- // enable uart0
- ldr r0, uart0_base
- ldr r1, atomic_set
- add r0, r0, r1
- mov r1, #1
- str r1, [r0, #0x30] // UART0_UARTCR
- // enable FIFO
- lsl r1, r1, #4
- str r1, [r0, #0x2c] // UART0_UARTLCR_H
- // set baud rate dividers
- mov r1, #67
- str r1, [r0, #0x24] // UART0_UARTIBRD
- mov r1, #52
- str r1, [r0, #0x28] // UART0_UARTFBRD
- // setup uart0
- mov r1, #3 // WLEN = 8
- lsl r1, r1, #5
- str r1, [r0, #0x2c] // UART0_UARTLCR_H
+ str r0, [r3, r1] // RESETS: RESET
- pop {r4, r5, pc}
-
-unreset:
- // unreset subsystems specified by r0
- // args: bit mask to specify the subsystems to unreset
- // return: the bit mask same as the arg
- ldr r1, resets_base
- ldr r2, atomic_clr
- add r1, r1, r2
- str r0, [r1, #0] // RESETS_RESET
- bx lr
-
-wait_unreset:
- // wait for subsystems specified by r0 to reset done
- // args: bit mask to specify the subsystems to wait for
- // return: void
- ldr r1, resets_base
reset_chk:
- ldr r2, [r1, #0x8] // RESETS_RESET_DONE
- and r0, r0, r2
+ ldr r1, [r3, #0x8] // RESETS: RESET_DONE
+ and r0, r0, r1
beq reset_chk
- bx lr
-
- .global putchar
-putchar:
-uart0_write:
- push {r4, r5, r6, r7, lr}
- mov r4, #0xFF
- and r4, r4, r0
- ldr r5, uart0_base
- mov r6, #32 // TXFF
-uart0_txff:
- ldr r7, [r5, #0x18] // UART0_UARTFR
- and r7, r7, r6
- bne uart0_txff
- str r4, [r5, #0] // UART0_UARTDR
- pop {r4, r5, r6, r7, pc}
-
- .global getchar
-getchar:
-uart0_read:
- push {r4, r5, r6, lr}
- ldr r4, uart0_base
- mov r5, #16
-uart0_rxfe:
- ldr r6, [r4, #0x18] // UART0_UARTFR
- and r6, r6, r5
- bne uart0_rxfe
- ldr r0, [r4, #0] // UART0_UARTDR
- mov r4, #0xFF
- and r0, r0, r4
- pop {r4, r5, r6, pc}
-
- .global print
- // void print(char *);
-print:
- push {r4, r5, lr}
- mov r4, r0
- mov r5, #0xFF
-print_loop:
- ldrb r1, [r4, #0]
- and r1, r1, r5
- beq print_end
- mov r0, r1
- bl uart0_write
- add r4, r4, #1
- b print_loop
-print_end:
- pop {r4, r5, pc}
-
- .global printh
- // void printh(uint32_t);
- // print in hex
-printh:
- push {r4, r5, r6, lr}
- mov r4, r0
- mov r5, #0xF
- mov r6, #28
-printh_loop:
- mov r0, r4
- lsr r0, r0, r6
- and r0, r0, r5
- cmp r0, #10
- blt printh_low
- add r0, #'A' - 10
- b printh_high
-printh_low:
- add r0, #'0'
-printh_high:
- bl putchar
- sub r6, r6, #4
- bge printh_loop
- pop {r4, r5, r6, pc}
-
- .global ldr
- // uint32_t ldr(uint32_t addr)
- // load content at addr
-ldr:
- ldr r0, [r0, #0]
- bx lr
-
-
-
-led_pr:
- // print register with 2 leds
- push {r0, r1, r2, r4, lr}
- mov r4, r0
- mov r1, #32
-led_pr_loop:
- mov r2, #1
- and r2, r2, r4
- beq led_pr_0
- bl led_p1
- b led_pr_1
-led_pr_0:
- bl led_p0
-led_pr_1:
- lsr r4, r4, #1
- sub r1, #1
- bne led_pr_loop
- pop {r0, r1, r2, r4, pc}
-
-led_p0:
- // blink led on gpio22
- push {r0, lr}
- mov r0, #1
- lsl r0, r0, #22
- bl led_blink
- pop {r0, pc}
+ // set gpio functions
+ ldr r3, io_bank0_base
+ mov r0, #5 // sio
+ mov r1, #0xcc
+ str r0, [r3, r1] // IO_BANK0: GPIO25_CTRL
-led_p1:
- // blink led on gpio24
- push {r0, lr}
+ // enable gpio output
+ ldr r3, sio_base
mov r0, #1
- lsl r0, r0, #24
- bl led_blink
- pop {r0, pc}
-
- .global led_p2
-led_p2:
- // blink led on gpio22 and gpio24
- push {r0, lr}
- mov r0, #5
- lsl r0, r0, #22
- bl led_blink
- pop {r0, pc}
+ lsl r0, r0, #25 // gpio25
+ str r0, [r3, #0x24] // SIO: GPIO_OE
-led_blink:
- push {r0, r4, r5, lr}
+ // blink led on gpio25
ldr r4, sio_base
mov r5, r0
+loop:
str r5, [r4, #0x10] // SIO_GPIO_OUT_SET
bl delay
str r5, [r4, #0x18] // SIO_GPIO_OUT_CLR
bl delay
- pop {r0, r4, r5, pc}
+ b loop
- .global delay
delay:
- push {r0}
mov r0, #1
- lsl r0, r0, #22
-del_loop:
+ lsl r0, r0, #20
+delay_loop:
sub r0, r0, #1
- bne del_loop
- pop {r0}
+ bne delay_loop
bx lr
// data
diff --git a/ex1/memmap.ld b/ex1/memmap.ld
@@ -11,10 +11,9 @@ SECTIONS
. = 0x100;
} > FLASH
- .text : AT(ORIGIN(FLASH) + 0x100){
+ .text : {
*(.vectors)
*(.text)
- _etext = .;
- } > SRAM
+ } > FLASH
}
