commit 92347b13b0f859dc4bec5f746533b50715378387
parent 6eb004dd7179a8872181c4a80794d531a882851b
Author: Matsuda Kenji <info@mtkn.jp>
Date: Wed, 12 Apr 2023 16:17:11 +0900
delete unnecessary items
Diffstat:
4 files changed, 0 insertions(+), 253 deletions(-)
diff --git a/Makefile b/Makefile
@@ -14,11 +14,7 @@ all: led.uf2
clean:
rm -f *.o *.elf *.uf2 *.bin
- rm -f boot2_crc.s
rm -f bincrc bin2uf2
- rm -f boot2/*.o
- rm -f boot2/*.bin
- rm -f boot2/boot2_crc.s
boot2.o: boot2.s
$(AS) $(ASFLAGS) -o boot2.o boot2.s
diff --git a/boot2/boot2.s b/boot2/boot2.s
@@ -1,161 +0,0 @@
-.cpu cortex-m0plus
-.thumb
-
- .global boot2
- .thumb_func
-boot2:
- push {r4, lr}
-
- // setup QSPI pad
- ldr r4, pads_qspi_base
- ldr r1, =(0 << 4 | 0 << 1 | 1) // 2mA, schmitt off, slew fast
- str r1, [r4, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
-
- // r4 should not be changed from this point on
- ldr r4, xip_ssi_base
-
- // set SSI standard SPI
- // disable SSI
- mov r1, #0
- str r1, [r4, #0x8] // SSI: SSIENR
- //set divider
- mov r1, #0x2
- str r1, [r4, #0x14] // SSI: BAUDR
- // set 1-cycle sample delay.
- mov r1, #1
- mov r2, #0xf0
- str r1, [r4, r2] // SSI: RX_SAMPLE_DLY
- // setup SSI
- ldr r1, =(7 << 16 | 3 << 8) // 8bit data frame size, eeprom
- str r1, [r4, #0] // SSI: CTRLR0
- mov r1, #0 // NDF = 0
- str r1, [r4, #0x4] // SSI: CTRLR1
- // enable SSI
- mov r1, #1
- str r1, [r4, #0x8] // SSI: SSIENR
-
- // set flash QSPI
- // write enable
- mov r1, #0x06 // write enable
- str r1, [r4, #0x60] // SSI: DR0
- bl wait_ssi
- ldr r1, [r4, #0x60] // SSI: DR0
- // enable QSPI
- mov r1, #0x31 // write status register-2
- str r1, [r4, #0x60] // SSI: DR0
- mov r1, #0x2 // quad enable
- str r1, [r4, #0x60] // SSI: DR0
- bl wait_ssi
- ldr r1, [r4, #0x60] // SSI: DR0
- ldr r1, [r4, #0x60] // SSI: DR0
-
-wait_sreg:
- mov r1, #0x5 // read status register-1
- // This str is required twice if TMOD = 0.
- // In this case, /CS signal is set to high just
- // after the first str instruction and the flash
- // doesn't shift out the status register.
- // On the other hand, If TMOD = 3 (eeprom),
- // then the /CS is kept to low until NDF + 1
- // data frames are captured.
- // Shiran Kedo.
- str r1, [r4, #0x60] // SSI: DR0
- bl wait_ssi
- ldr r1, [r4, #0x60] // SSI: DR0
- mov r2, #1 // BUSY flag
- tst r1, r2
- bne wait_sreg
-
- // set SSI QSPI and XIP
- // disable SSI
- mov r1, #0
- str r1, [r4, #0x8] // SSI: SSIENR
- // set up QSPI
- // DFS is said to be the number of clocks of a data frame - 1.
- // But in QSPI mode, a frame is 32 bits and is transfered in 8 clocks.
- // However, if DFS is set to 7, It doesn't work.
- // Maybe this is a bug of the documentation.
- ldr r1, =(2 << 21 | 31 << 16 | 3 << 8) // quad, 32bit data frame, eeprom
- str r1, [r4, #0] // SSI: CTRLR0
- // setup xip
- ldr r1, =(4 << 11 | 2 << 8 | 8 << 2 | 1 << 0)
- mov r2, #0xf4
- str r1, [r4, r2] // SSI: SPI_CTRLR0
- // re-enable SSI
- mov r1, #1
- str r1, [r4, #0x8] // SSI: SSIENR
-
- // first read from flash
- // set flash continuous read
- mov r1, #0xeb // fast read quad i/o
- str r1, [r4, #0x60] // SSI: DR0
- // continuous read is not documented in w25q16j datasheet...
- // it says mode bits should be Fxh (x: don't care)...
- // in w2580bv datasheet, these bits are said to be 0bxx10xxxx.
- // why w25q16j lacks the description?
- mov r1, #0x20
- str r1, [r4, #0x60] // SSI: DR0
- bl wait_ssi
-
- // set SIP continuous read
- // disable SSI
- mov r1, #0
- str r1, [r4, #0x8] // SSI: SSIENR
- // the command bit is not documented.
- ldr r1, =(0x20 << 24 | 4 << 11 | 0 << 8 | 8 << 2 | 2 << 0)
- mov r2, #0xf4
- str r1, [r4, r2] // SSI: SPI_CTRLR0
- // re-enable SSI
- mov r1, #1
- str r1, [r4, #0x8] // SSI: SSIENR
-
- ldr r2, boot2_end
- ldr r3, sram_base
- ldr r0, =0x100 // copy first 256 words.
-sram_cpy:
- ldr r1, [r2, #0]
- str r1, [r3, #0]
- add r2, r2, #0x4
- add r3, r3, #0x4
- sub r0, r0, #0x4
- bne sram_cpy
-
- // exit from boot2
- pop {r4}
- pop {r0}
- cmp r0, #0
- beq initial_boot
- bx r0
-initial_boot:
- ldr r0, sram_base
- ldr r1, m0plus_vtor
- str r0, [r1, #0] // M0PLUS: VTOR
- ldr r1, [r0, #4] // entry point
- ldr r0, [r0, #0] // stack pointer
- mov sp, r0
- bx r1
-
-wait_ssi:
- // asumes that r4 is xip_ssi_base
- ldr r1, [r4, #0x28] // SSI: SR
- mov r2, #4 // TFE
- tst r1, r2
- beq wait_ssi
- mov r2, #1 // BUSY
- tst r1, r2
- bne wait_ssi
- bx lr
-
- .align 2
-boot2_end:
- .word 0x10000000 + 0x100
-xip_ssi_base:
- .word 0x18000000
-sram_base:
- .word 0x20000000
-pads_qspi_base:
- .word 0x40020000
-m0plus_vtor:
- .word 0xe0000000 + 0xed08
-literals:
- .ltorg
diff --git a/boot2/boot2_generic.s b/boot2/boot2_generic.s
@@ -1,39 +0,0 @@
-.cpu cortex-m0plus
-.thumb
-
-.equ XIP_BASE, 0x10000000
-.equ XIP_SSI_BASE, 0x18000000
-.equ PPB_BASE, 0xe0000000
-
-boot2:
- ldr r4, =XIP_SSI_BASE
-
- mov r1, #0
- str r1, [r4, #0x8] // SSI: SSIENR
-
- mov r1, #4
- str r1, [r4, #0x14] // SSI: BAUDR
- mov r1, #1
- mov r2, #0xf0
- str r1, [r4, r2] // SSI: RX_SAMPLE_DLY
- ldr r1, =((31 << 16) | (3 << 8))
- str r1, [r4, #0x0] // SSI: CTRLR0
-
- mov r1, #0 // NDF = 0
- str r1, [r4, #0x4] // SSI: CTRLR1
-
- ldr r1, =((0x03 << 24) | (2 << 8) | (6 << 2))
- mov r0, #0xf4
- str r1, [r4, r0] // SSI: SPI_CTRLR0
-
- mov r1, #1
- str r1, [r4, #0x8] // SSI: SSIENR
-
- // exit from boot2
- ldr r0, =(XIP_BASE + 0x100)
- ldr r1, =(PPB_BASE + 0xed08)
- str r0, [r1, #0] // M0PLUS: VTOR
- ldr r1, [r0, #4]
- ldr r0, [r0, #0]
- mov sp, r0
- bx r1
diff --git a/boot2/boot2_sram.s b/boot2/boot2_sram.s
@@ -1,49 +0,0 @@
-.cpu cortex-m0plus
-.thumb
-
-.equ XIP_BASE, 0x10000000
-.equ XIP_SSI_BASE, 0x18000000
-.equ SRAM_BASE, 0x20000000
-.equ PPB_BASE, 0xe0000000
-
-boot2:
- ldr r4, =XIP_SSI_BASE
-
- // set SSI standard SPI
- mov r1, #0
- str r1, [r4, #0x8] // SSI: SSIENR
- mov r1, #4
- str r1, [r4, #0x14] // SSI: BAUDR
- mov r1, #1
- mov r2, #0xf0
- str r1, [r4, r2] // SSI: RX_SAMPLE_DLY
- ldr r1, =((31 << 16) | (3 << 8))
- str r1, [r4, #0x0] // SSI: CTRLR0
- mov r1, #0 // NDF = 0
- str r1, [r4, #0x4] // SSI: CTRLR1
- ldr r1, =((0x03 << 24) | (2 << 8) | (6 << 2))
- mov r0, #0xf4
- str r1, [r4, r0] // SSI: SPI_CTRLR0
- mov r1, #1
- str r1, [r4, #0x8] // SSI: SSIENR
-
- // copy program data from flash to sram
- ldr r2, =(XIP_BASE + 0x100)
- ldr r3, =SRAM_BASE
- ldr r0, =0x1000 // how to get the program size?
-sram_cpy:
- ldr r1, [r2, #0]
- str r1, [r3, #0]
- add r2, r2, #0x4
- add r3, r3, #0x4
- sub r0, r0, #0x4
- bne sram_cpy
-
- // exit from boot2
- ldr r0, =SRAM_BASE
- ldr r1, =(PPB_BASE + 0xed08)
- str r0, [r1, #0] // M0PLUS: VTOR
- ldr r1, [r0, #4]
- ldr r0, [r0, #0]
- mov sp, r0
- bx r1
