commit 87726853f36f7a327ce8956a864a0432d38e1e28
parent b5a8285479ca22755f493e59f99d6ff882df1363
Author: Matsuda Kenji <info@mtkn.jp>
Date: Thu, 16 Mar 2023 15:19:18 +0900
use xosc
Diffstat:
| M | main.s | | | 64 | +++++++++++++++++++++++++++++++++++++++++++++++++--------------- |
1 file changed, 49 insertions(+), 15 deletions(-)
diff --git a/main.s b/main.s
@@ -24,29 +24,20 @@ xosc_stable:
lsr r1, r1, #31
beq xosc_stable
- // set ref clock to xosc
- ldr r0, clocks_base
- mov r1, #2
- str r1, [r0, #0x30] // CLOCKS_CLK_REF_CTRL
-
- // set sys clock to ref
- mov r1, #0
- str r1, [r0, #0x3c] // CLOCKS_CLK_SYS_CTRL
-
- // reset gpio
+ // reset gpio and pll
ldr r0, resets_base
ldr r1, atomic_clr
add r0, r0, r1
mov r2, #0x1
- lsl r1, r2, #5
- lsl r2, r2, #22
+ lsl r1, r2, #5 // io_bank0
+ lsl r2, r2, #12 // pll_sys
add r1, r1, r2
- str r1, [r0, #0]
+ str r1, [r0, #0] // RESETS_RESET
// check if reset is done
ldr r0, resets_base
reset_chk:
- ldr r2, [r0, #0x8]
+ ldr r2, [r0, #0x8] // RESETS_RESET_DONE
and r1, r1, r2
beq reset_chk
@@ -56,12 +47,52 @@ reset_chk:
mov r1, #5
str r1, [r0, #0]
- // enable output
+ // enable gpio output
ldr r0, sio_base
mov r1, #1
lsl r1, r1, #24
str r1, [r0, #0x24]
+ // set feedback divider
+ ldr r0, pll_sys_base
+ mov r1, #0x14
+ lsl r1, r1, #4
+ str r1, [r0, #0x8]
+
+ // power on pll
+ ldr r1, atomic_clr
+ add r0, r0, r1
+ mov r1, #33
+ str r1, [r0, #0x4] // PLL_PWR
+
+ // wait for pll locking
+ ldr r0, pll_sys_base
+pll_lock:
+ ldr r1, [r0, #0] // PLL_CS
+ lsr r1, r1, #31
+ beq pll_lock
+
+ // set post dividers
+ ldr r1, atomic_set
+ add r0, r0, r1
+ mov r1, #1
+ lsl r1, r1, #4
+ add r1, r1, #1
+ lsl r1, r1, #12
+ str r1, [r0, #0xc] // PLL_PRIM
+
+ // turn on post dividers
+ ldr r0, pll_sys_base
+ ldr r1, atomic_clr
+ add r0, r0, r1
+ mov r1, #8
+ str r1, [r0, #0x4] // PLL_PWR
+
+ // set sys clock to pll_sys
+ ldr r0, clocks_base
+ mov r1, #1
+ str r1, [r0, #0x3c] // CLOCKS_CLK_SYS_CTRL
+
loop:
bl led_blink
b loop
@@ -112,6 +143,9 @@ io_bank0_base:
xosc_base:
.word 0x40024000
+pll_sys_base:
+ .word 0x40028000
+
rosc_base:
.word 0x40060000
