rp2040

commit 7ac02b3494f4e08b01f07991ae910dd11baf5a1c
parent f54b95e177d885028b09e1ab7ce368f6db3240c5
Author: Matsuda Kenji <info@mtkn.jp>
Date:   Tue,  4 Apr 2023 07:48:38 +0900

copy boot2 from sdk and compile.
It worked

Diffstat:
M
boot2/boot2_w25q.S
 | 
64
+++++++++++++---------------------------------------------------

1 file changed, 13 insertions(+), 51 deletions(-)
diff --git a/boot2/boot2_w25q.S b/boot2/boot2_w25q.S
@@ -1,6 +1,7 @@
 .equ XIP_SSI_BASE,   0x18000000
 .equ PADS_QSPI_BASE, 0x40020000
 .equ PPB_BASE,       0xe0000000
+.equ XIP_BASE,       0x10000000
 
 .syntax unified
 .cpu cortex-m0plus
@@ -29,11 +30,11 @@ _stage2_boot:
 
     // Disable SSI to allow further config
     movs r1, #0
-    str r1, [r3, #0x8]
+    str r1, [r3, #0x8] // SSI: SSIENR
 
     // Set baud rate
-    movs r1, #4
-    str r1, [r3, #0x14]
+    movs r1, #2
+    str r1, [r3, #0x14] // SSI: BAUDR
 
     // Set 1-cycle sample delay. If 4 == 2 then this means,
     // if the flash launches data on SCLK posedge, we capture it at the time that
@@ -42,24 +43,19 @@ _stage2_boot:
     // 4 > 2 this pretty much has no effect.
 
     movs r1, #1
-    ldr r2, =0xf0  // == 0xf0 so need 8 bits of offset significance
+    movs r2, #0xf0
     str r1, [r3, r2]
 
 
 // On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
 // (i.e. turn WPn and HOLDn into IO2/IO3)
 program_sregs:
-    movs r1, #7
-    lsls r1, r1, #16
-    movs r2, #0
-    lsls r2, r2, #8
-    adds r1, r1, r2
-
-    str r1, [r3, #0]
+    ldr r1, =((7 << 16) | (0 << 8))
+    str r1, [r3, #0] // SSI: CTRLR0
 
      // Enable SSI and select slave 0
     movs r1, #1
-    str r1, [r3, #0x8]
+    str r1, [r3, #0x8] // SSI: SSIENR
 
     // Check whether SR needs updating
     movs r0, #0x35
@@ -109,30 +105,13 @@ skip_sreg_programming:
 // of the read, the important part is the mode bits.
 
 dummy_read:
-    movs r1, #0x2
-    lsls r1, r1, #21
-    movs r2, #31
-    lsls r2, r2, #16
-    adds r1, r1, r2
-    movs r2, #3
-    lsls r2, r2, #8
-    adds r1, r1, r2
-
+    ldr r1, =((2 << 21) | (31 << 16) | (3 << 8))
     str r1, [r3, #0x0]
 
     movs r1, #0x0                    // NDF=0 (single 32b read)
     str r1, [r3, #0x4]
 
-    movs r1, #8
-    lsls r1, r1, #2
-    movs r2, #4
-    lsls r2, r2, #11
-    adds r1, r1, r2
-    movs r2, #2
-    lsls r2, r2, #8
-    adds r1, r1, r2
-    adds r1, #1
-
+    ldr r1, =((8 << 2) | (4 << 11) | (2 << 8) | (1 << 0))
     ldr r0, =(XIP_SSI_BASE + 0xf4)  // SPI_CTRL0 Register
     str r1, [r0]
 
@@ -159,20 +138,7 @@ dummy_read:
 //      INST_L_0_BITS   {ADDR[23:0],XIP_CMD[7:0]}       Load "mode bits" into XIP_CMD
 //      Anything else   {XIP_CMD[7:0],ADDR[23:0]}       Load SPI command into XIP_CMD
 configure_ssi:
-    movs r1, #0xa0
-    lsls r1, r1, #24
-    movs r2, #8
-    lsls r2, #2
-    adds r1, r1, r2
-    movs r2, #4
-    lsls r2, r2, #11
-    adds r1, r1, r2
-    movs r2, #0
-    lsls r2, r2, #8
-    adds r1, r1, r2
-    adds r1, #2
-
-    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r1, =((0xa0 << 24) | (8 << 2) | (4 << 11) | (0 << 8) | (2 << 0))
     ldr r0, =(XIP_SSI_BASE + 0xf4)
     str r1, [r0]
 
@@ -189,12 +155,8 @@ check_return:
     beq vector_into_flash
     bx r0
 vector_into_flash:
-    ldr r0, =XIP_BASE
-    ldr r1, =0x100
-    adds r0, r0, r1
-    ldr r1, =PPB_BASE
-    ldr r2, =0xed08
-    adds r1, r1, r2
+    ldr r0, =(XIP_BASE + 0x100)
+    ldr r1, =(PPB_BASE + 0xed08)
     str r0, [r1]
     ldmia r0, {r0, r1}
     msr msp, r0