commit 7470441b9933e937d12bc2771c80a5339d6723e7
parent e6965362328b88220647bb1b1e51b0410d8abf25
Author: Matsuda Kenji <info@mtkn.jp>
Date: Sun, 9 Apr 2023 11:02:32 +0900
copy flash program to sram
Diffstat:
3 files changed, 54 insertions(+), 20 deletions(-)
diff --git a/Makefile b/Makefile
@@ -19,13 +19,13 @@ clean:
rm -f bincrc bin2uf2
rm -f boot2/*.o
rm -f boot2/*.bin
- rm -f boot2/boot2_crc.S
+ rm -f boot2/boot2_crc.s
start.o: start.s
$(AS) $(ASFLAGS) -o start.o start.s
-boot2_crc.o: boot2/boot2_sram.s bincrc
- $(AS) $(ASFLAGS) -o boot2/boot2.o boot2/boot2_sram.s
+boot2_crc.o: boot2/boot2.s bincrc
+ $(AS) $(ASFLAGS) -o boot2/boot2.o boot2/boot2.s
$(OBJCOPY) -O binary boot2/boot2.o boot2/boot2.bin
./bincrc boot2/boot2.bin boot2/boot2_crc.s
$(AS) $(ASFLAGS) -o boot2_crc.o boot2/boot2_crc.s
diff --git a/boot2/boot2.s b/boot2/boot2.s
@@ -3,10 +3,13 @@
.equ XIP_BASE, 0x10000000
.equ XIP_SSI_BASE, 0x18000000
+.equ SRAM_BASE, 0x20000000
.equ PADS_QSPI_BASE, 0x40020000
.equ PPB_BASE, 0xe0000000
boot2:
+ push {r4, lr}
+
ldr r4, =PADS_QSPI_BASE
ldr r1, =(2 << 4 | 1) // 8mA, slew fast
str r1, [r4, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
@@ -101,8 +104,25 @@ wait_sreg:
mov r1, #1
str r1, [r4, #0x8] // SSI: SSIENR
+ ldr r2, =(XIP_BASE + 0x100)
+ ldr r3, =SRAM_BASE
+ ldr r0, =0x1000
+sram_cpy:
+ ldr r1, [r2, #0]
+ str r1, [r3, #0]
+ add r2, r2, #0x4
+ add r3, r3, #0x4
+ sub r0, r0, #0x4
+ bne sram_cpy
+
// exit from boot2
- ldr r0, =(XIP_BASE + 0x100)
+ pop {r4}
+ pop {r0}
+ cmp r0, #0
+ beq initial_boot
+ bx r0
+initial_boot:
+ ldr r0, =SRAM_BASE
ldr r1, =(PPB_BASE + 0xed08)
str r0, [r1, #0] // M0PLUS: VTOR
ldr r1, [r0, #4] // entry point
diff --git a/mach.s b/mach.s
@@ -1,7 +1,7 @@
.section .text
.global init
init:
- push {r4, r5, r6, lr}
+ push {lr}
// unreset gpio and pll_sys and uart0
mov r1, #1
lsl r0, r1, #5 // io_bank0
@@ -119,25 +119,33 @@ pll_lock:
lsl r1, r1, #5
str r1, [r0, #0x2c] // UART0_UARTLCR_H
- mov r4, #16
- mov r5, #0
- ldr r6, xip_ssi_base
-read_loop:
- str r5, [r6, #0x60] // SSI: DR0
-wait_ssi_loop:
- ldr r1, [r6, #0x28] // SSI: SR
- mov r2, #1
- and r1, r2 // BUSY
- bne wait_ssi_loop
- ldr r0, [r6, #0x60] // SSI: DR0
+debug:
+ ldr r4, xip_base
+ ldr r5, =(0x100)
+ add r4, r4, r5
+ mov r5, #4
+debug_loop:
+ ldr r0, [r4, #0]
+ bl printh
+ mov r0, #0x0A
+ bl putchar
+ add r4, r4, #4
+ sub r5, #1
+ bne debug_loop
+
+debugs:
+ ldr r4, sram_base
+ mov r5, #4
+debug_loops:
+ ldr r0, [r4, #0]
bl printh
mov r0, #0x0A
bl putchar
- add r5, r5, #0x4
- sub r4, #1
- bne read_loop
+ add r4, r4, #4
+ sub r5, #1
+ bne debug_loops
- pop {r4, r5, r6, pc}
+ pop {pc}
unreset:
// unreset subsystems specified by r0
@@ -396,9 +404,15 @@ atomic_set:
atomic_clr:
.word 0x00003000
+xip_base:
+ .word 0x10000000
+
xip_ssi_base:
.word 0x18000000
+sram_base:
+ .word 0x20000000
+
clocks_base:
.word 0x40008000
