rp2040

commit 50b7abdbdbd20e8dc67fdfae4da8ea8fefa68c6b
parent 4db5a73bf8811b1e44c1cc5ef977f525f5723afa
Author: Matsuda Kenji <info@mtkn.jp>
Date:   Wed, 13 Aug 2025 07:48:24 +0900

disable uart FIFO

Diffstat:
M
ex3_spi/main.s
 | 
6
+++---

1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/ex3_spi/main.s b/ex3_spi/main.s
@@ -142,8 +142,8 @@ wait_vco:
 	ldr r1, atomic_set
 	add r1, r1, #0x30
 	str r0, [r3, r1] // UART: UARTCR
-	// enable FIFO and set format
-	ldr r0, =(3 << 5 | 1 << 4) // WLEN = 8, FEN = 1
+	// disable FIFO and set format
+	ldr r0, =(3 << 5 | 0 << 4) // WLEN = 8, FEN = 0
 	str r0, [r3, #0x2c] // UART: UARTLCR_H
 
 	// enable uart interrupt in cpu
@@ -158,7 +158,7 @@ wait_vco:
 	ldr r1, uart0_base
 	// according to sdk's src/rp2_common/hardware_uart/include/hardware/uart.h
 	// receive interrupt needs RTIM bit masked
-	mov r2, #(1<<6|1<<4) // RTIM | RXIM
+	mov r2, #(1<<4) // RTIM | RXIM
 	str r2, [r1, #0x38] // UART: UARTIMSC
 	// set fifo level to 0
 	mov r2, #0