rp2040

commit 2e8ca876a44bfb9dc0dd47d6aef9d4759d6a5fe1
parent 2fe87fbb0f00039bfa96dd92a6781fc24152b8cd
Author: Matsuda Kenji <info@mtkn.jp>
Date:   Wed, 21 Feb 2024 17:24:52 +0900

delete unnecessary lines

Diffstat:
M
ex2/main.s
 | 
28
+++++++++-------------------

1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/ex2/main.s b/ex2/main.s
@@ -25,21 +25,10 @@ unreset_chk:
 	str r0, [r3, r1] // IO_BANK0: GPIO0_CTRL
 	mov r1, #0xc
 	str r0, [r3, r1] // IO_BANK0: GPIO1_CTRL
-	mov r0, #5 // sio
-	mov r1, #0xc4
-	str r0, [r3, r1] // IO_BANK0: GPIO24_CTRL
-	mov r1, #0xcc
-	str r0, [r3, r1] // IO_BANK0: GPIO25_CTRL
-
-	// enable gpio output
-	ldr r3, sio_base
-	mov r0, #3
-	lsl r0, r0, #24 // gpio25 | gpio24
-	str r0, [r3, #0x24] // SIO: GPIO_OE
 
 	// setup xosc
 	ldr r3, xosc_base
-	mov r0, #47 // start up delay for 12MHz xosc
+	mov r0, #47 // start up delay for 12MHz rosc (xosc?)
 	str r0, [r3, #0xc] // XOSC: STARTUP
 	ldr r0, =(0xfab << 12 | 0xaa0)
 	str r0, [r3, #0] // XOSC: CTRL
@@ -79,20 +68,21 @@ wait_vco:
 	lsl r0, r0, #11
 	str r0, [r3, #0x48] // CLOCKS: CLK_PERI_CTRL
 
-	// enable uart0
+	// setup uart0
 	ldr r3, uart0_base
-	ldr r0, =(1 << 9 | 1 << 8 | 1) // RXE | TXE | UARTEN
-	ldr r1, atomic_set
-	add r1, r1, #0x30
-	str r0, [r3, r1] // UART: UARTCR
 	// set baudrate 115200
 	// BDRI = 72, BDRF = 0.157 (10 / 64)
 	mov r0, #72
 	str r0, [r3, #0x24] // UART: UARTIBRD
 	mov r0, #10
 	str r0, [r3, #0x28] // UART: UARTFBRD
+	// enable uart0
+	mov r0, #1 // UARTEN
+	ldr r1, atomic_set
+	add r1, r1, #0x30
+	str r0, [r3, r1] // UART: UARTCR
 	// enable FIFO and set format
-	ldr r0, =(3 << 5 | 1 << 4) // WLEN = 8
+	ldr r0, =(3 << 5 | 1 << 4) // WLEN = 8, FEN = 1
 	str r0, [r3, #0x2c] // UART: UARTLCR_H
 
 loop:
@@ -102,7 +92,7 @@ loop:
 
 // functions
 
-	// print r0 in hex
+	// print r0 in hex for debugging.
 printh:
 	push {r4, r5, r6, r7, lr}
 	mov r4, r0