rp2040

commit 1d6cce69cae52839daca66bab14030a82430075d
parent 0756ba9580dbea415d64cee5d98d3724ac0135a2
Author: Matsuda Kenji <info@mtkn.jp>
Date:   Fri, 24 Mar 2023 10:37:19 +0900

fix bug, and finally it works
normal write to UARTCT cleared the RXE and TXE flag.
I needed to set it ORing with the original value,
or to use the atomic set register

Diffstat:
M
main.s
 | 
9
++++-----

1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/main.s b/main.s
@@ -97,11 +97,12 @@ pll_lock:
 	ldr r0, clocks_base
 	mov r1, #1
 	lsl r1, r1, #11
-	add r1, r1, #128 // xosc_clksrc
 	str r1, [r0, #0x48] // CLOCKS_CLK_PERI_CTRL
 	
 	// enable uart0
 	ldr r0, uart0_base
+	ldr r1, atomic_set
+	add r0, r0, r1
 	mov r1, #1
 	str r1, [r0, #0x30] // UART0_UARTCR
 	// enable FIFO
@@ -118,8 +119,7 @@ pll_lock:
 	str r1, [r0, #0x2c] // UART0_UARTLCR_H
 
 loop:
-	bl p2
-	mov r0, #0x41
+	bl uart0_read
 	bl uart0_write
 	b loop
 
@@ -153,7 +153,6 @@ uart0_write:
 	ldr r5, uart0_base
 	mov r6, #32 // TXFF
 uart0_txff:
-	bl p0
 	ldr r7, [r5, #0x18] // UART0_UARTFR
 	and r7, r7, r6
 	bne uart0_txff
@@ -229,7 +228,7 @@ led_blink:
 
 delay:
 	mov r0, #1
-	lsl r0, r0, #25
+	lsl r0, r0, #22
 del_loop:
 	sub r0, r0, #1
 	bne del_loop