commit 0d22cee5039f57d7c55fc81c60ec9cc0cc01abca
parent e207284e1e04b23037e80ea0157ce702c045b9cf
Author: Matsuda Kenji <info@mtkn.jp>
Date: Sat, 8 Apr 2023 09:57:19 +0900
nanka ugoita
TMOD should be EEPROM
Diffstat:
3 files changed, 35 insertions(+), 38 deletions(-)
diff --git a/Makefile b/Makefile
@@ -27,8 +27,8 @@ start.o: start.s
boot2_crc.o: boot2/boot2_crc.S
$(AS) $(ASFLAGS) -o boot2_crc.o boot2/boot2_crc.S
-boot2/boot2_crc.S: boot2/boot2.s bincrc
- $(AS) $(ASFLAGS) -o boot2/boot2.o boot2/boot2.s
+boot2/boot2_crc.S: boot2/boot2_generic.s bincrc
+ $(AS) $(ASFLAGS) -o boot2/boot2.o boot2/boot2_generic.s
$(OBJCOPY) -O binary boot2/boot2.o boot2/boot2.bin
./bincrc boot2/boot2.bin boot2/boot2_crc.S
diff --git a/boot2/boot2.s b/boot2/boot2.s
@@ -11,15 +11,15 @@ boot2:
ldr r1, =(2 << 4 | 1) // 8mA, slew fast
str r1, [r4, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK
- // r4 should not be changed
+ // r4 should not be changed from this point on
ldr r4, =XIP_SSI_BASE
// set SSI standard SPI
- // disable ssi
+ // disable SSI
mov r1, #0
str r1, [r4, #0x8] // SSI: SSIENR
//set divider
- ldr r1, =0x2 // This is 2 in sdk
+ mov r1, #0x2 // This is 2 in sdk
str r1, [r4, #0x14] // SSI: BAUDR
// set 1-cycle sample delay.
mov r1, #1
@@ -28,7 +28,7 @@ boot2:
// setup sregs
ldr r1, =((7 << 16) | (0 << 8)) // 8bit data frame size, tx and rx
str r1, [r4, #0] // SSI: CTRLR0
- // enable ssi
+ // enable SSI
mov r1, #1
str r1, [r4, #0x8] // SSI: SSIENR
@@ -61,7 +61,7 @@ wait_sreg:
bne wait_sreg
// set SSI QSPI and XIP
- // disable ssi
+ // disable SSI
mov r1, #0
str r1, [r4, #0x8] // SSI: SSIENR
// set up quad spi
@@ -73,7 +73,7 @@ wait_sreg:
ldr r1, =((4 << 11) | (2 << 8) | (8 << 2) | (1 << 0))
mov r2, #0xf4
str r1, [r4, r2] // SSI: SPI_CTRLR0
- // re-enable ssi
+ // re-enable SSI
mov r1, #1
str r1, [r4, #0x8] // SSI: SSIENR
@@ -90,14 +90,14 @@ wait_sreg:
bl wait_ssi
// set SIP continuous read
- // disable ssi
+ // disable SSI
mov r1, #0
str r1, [r4, #0x8] // SSI: SSIENR
// the command bit is not documented.
ldr r1, =((0x20 << 24) | (4 << 11) | (0 << 8) | (8 << 2) | (2 << 0))
mov r2, #0xf4
str r1, [r4, r2] // SSI: SPI_CTRLR0
- // re-enable ssi
+ // re-enable SSI
mov r1, #1
str r1, [r4, #0x8] // SSI: SSIENR
@@ -105,7 +105,7 @@ wait_sreg:
ldr r0, =(XIP_BASE + 0x100)
ldr r1, =(PPB_BASE + 0xed08)
str r0, [r1, #0] // M0PLUS: VTOR
- ldr r1, [r0, #0x4] // entry point
+ ldr r1, [r0, #4] // entry point
ldr r0, [r0, #0] // stack pointer
mov sp, r0
bx r1
diff --git a/boot2/boot2_generic.s b/boot2/boot2_generic.s
@@ -1,42 +1,39 @@
-.cpu cortex-m0
+.cpu cortex-m0plus
.thumb
-.equ XIP_BASE, 0x10000000
-.equ XIP_SSI_BASE, 0x18000000
-.equ PPB_BASE, 0xe0000000
+.equ XIP_BASE, 0x10000000
+.equ XIP_SSI_BASE, 0x18000000
+.equ PPB_BASE, 0xe0000000
-.thumb_func
boot2:
- push {lr}
-
- ldr r3, =XIP_SSI_BASE
+ ldr r4, =XIP_SSI_BASE
mov r1, #0
- str r1, [r3, #0x8] // SSI: SSIENR
-
- mov r1, #2
- str r1, [r3, #0x14] // SSI: BAUDR
- ldr r1, =((0 << 21) | (31 << 16) | (0 << 8))
- str r1, [r3, #0x0] // SSI: CTRLR0
+ str r1, [r4, #0x8] // SSI: SSIENR
- ldr r0, =0xf4
- ldr r1, =((0x03 << 24) | (0x2 << 8) | (6 << 2))
- str r1, [r3, r0] // SSI: SPI_CTRLR0
+ mov r1, #4
+ str r1, [r4, #0x14] // SSI: BAUDR
+ mov r1, #1
+ mov r2, #0xf0
+ str r1, [r4, r2] // SSI: RX_SAMPLE_DLY
+ ldr r1, =((31 << 16) | (3 << 8))
+ str r1, [r4, #0x0] // SSI: CTRLR0
mov r1, #0 // NDF = 0
- str r1, [r3, #0x4] // SSI: CTRLR1
+ str r1, [r4, #0x4] // SSI: CTRLR1
+
+ ldr r1, =((0x03 << 24) | (2 << 8) | (6 << 2))
+ mov r0, #0xf4
+ str r1, [r4, r0] // SSI: SPI_CTRLR0
mov r1, #1
- str r1, [r3, #0x8] // SSI: SSIENR
+ str r1, [r4, #0x8] // SSI: SSIENR
- pop {r0}
- cmp r0, #0
- beq vector_into_flash
- bx r0
-vector_into_flash:
+ // exit from boot2
ldr r0, =(XIP_BASE + 0x100)
ldr r1, =(PPB_BASE + 0xed08)
- str r0, [r1, #0x0] // M0PLUS: VTOR
- ldmia r0, {r0, r1}
- msr msp, r0
+ str r0, [r1, #0] // M0PLUS: VTOR
+ ldr r1, [r0, #4]
+ ldr r0, [r0, #0]
+ mov sp, r0
bx r1
