mach.s (5671B)
1 .cpu cortex-m0plus 2 .thumb 3 4 .section .vectors 5 vectors: 6 .word 0x20040000 // initial SP 7 .word (reset+1) // entry point 8 9 .section .text 10 .thumb_func 11 reset: 12 bl main 13 hang: 14 b hang 15 16 .global init 17 .thumb_func 18 init: 19 push {r4, r5, lr} 20 // unreset gpio and pll_sys and uart0 21 mov r1, #1 22 lsl r0, r1, #5 // io_bank0 23 lsl r1, r1, #12 // pll_sys 24 add r0, r0, r1 25 lsl r1, r1, #10 // uart0 26 add r0, r0, r1 27 bl unreset 28 bl wait_unreset 29 30 // set gpio functions 31 ldr r0, io_bank0_base 32 mov r1, #2 // uart0 33 mov r2, #5 // sio 34 add r0, r0, #0x4 // io_bank0_gpio0_ctrl 35 str r1, [r0, #0] // uart0 36 add r0, r0, #0x8 // #0xc io_bank0_gpio1_ctrl 37 str r1, [r0, #0] // uart0 38 add r0, r0, #0xa8 // #0xb4 io_bank0_gpio22_ctrl 39 str r2, [r0, #0] // sio 40 add r0, r0, #0x10 // #0xc4 io_bank0_gpio24_ctrl 41 str r2, [r0, #0] // sio 42 43 // enable gpio output 44 ldr r0, sio_base 45 mov r1, #5 46 lsl r1, r1, #22 // gpio22 and gpio24 47 str r1, [r0, #0x24] 48 49 // enable xosc 50 ldr r0, xosc_base 51 mov r1, #0xf 52 lsl r1, r1, #8 53 add r1, r1, #0xab 54 lsl r1, r1, #8 55 add r1, r1, #0xaa 56 lsl r1, r1, #4 57 str r1, [r0, #0] // XOSC_CTRL 58 59 // set xosc delay 60 mov r1, #47 61 str r1, [r0, #0xc] // XOSC_STARTUP 62 63 // wait for xosc startup 64 xosc_stable: 65 ldr r1, [r0, #0x4] // XOSC_STATUS 66 lsr r1, r1, #31 67 beq xosc_stable 68 69 // set pll feedback divider 70 ldr r0, pll_sys_base 71 mov r1, #125 72 str r1, [r0, #0x8] // PLL_FBDIV_INT 73 74 // power on pll 75 ldr r1, atomic_clr 76 add r0, r0, r1 77 mov r1, #33 // VCOPD | PD 78 str r1, [r0, #0x4] // PLL_PWR 79 80 // wait for pll locking 81 ldr r0, pll_sys_base 82 pll_lock: 83 ldr r1, [r0, #0] // PLL_CS 84 lsr r1, r1, #31 85 beq pll_lock 86 87 // set post dividers 88 ldr r0, pll_sys_base 89 ldr r1, atomic_clr 90 add r0, r0, r1 91 mov r1, #3 92 lsl r1, r1, #4 93 add r1, r1, #4 94 lsl r1, r1, #12 95 str r1, [r0, #0xc] // PLL_PRIM 96 97 // turn on post dividers 98 ldr r0, pll_sys_base 99 ldr r1, atomic_clr 100 add r0, r0, r1 101 mov r1, #8 102 str r1, [r0, #0x4] // PLL_PWR 103 104 // set sys clock to pll_sys 105 ldr r0, clocks_base 106 mov r1, #1 107 str r1, [r0, #0x3c] // CLOCKS_CLK_SYS_CTRL 108 // enable clk_peri 109 lsl r1, r1, #11 110 str r1, [r0, #0x48] 111 112 // enable clk_peri 113 ldr r0, clocks_base 114 mov r1, #1 115 lsl r1, r1, #11 116 str r1, [r0, #0x48] // CLOCKS_CLK_PERI_CTRL 117 118 // enable uart0 119 ldr r0, uart0_base 120 ldr r1, atomic_set 121 add r0, r0, r1 122 mov r1, #1 123 str r1, [r0, #0x30] // UART0_UARTCR 124 // enable FIFO 125 lsl r1, r1, #4 126 str r1, [r0, #0x2c] // UART0_UARTLCR_H 127 // set baud rate dividers 128 mov r1, #67 129 str r1, [r0, #0x24] // UART0_UARTIBRD 130 mov r1, #52 131 str r1, [r0, #0x28] // UART0_UARTFBRD 132 // setup uart0 133 mov r1, #3 // WLEN = 8 134 lsl r1, r1, #5 135 str r1, [r0, #0x2c] // UART0_UARTLCR_H 136 137 pop {r4, r5, pc} 138 139 unreset: 140 // unreset subsystems specified by r0 141 // args: bit mask to specify the subsystems to unreset 142 // return: the bit mask same as the arg 143 ldr r1, resets_base 144 ldr r2, atomic_clr 145 add r1, r1, r2 146 str r0, [r1, #0] // RESETS_RESET 147 bx lr 148 149 wait_unreset: 150 // wait for subsystems specified by r0 to reset done 151 // args: bit mask to specify the subsystems to wait for 152 // return: void 153 ldr r1, resets_base 154 reset_chk: 155 ldr r2, [r1, #0x8] // RESETS_RESET_DONE 156 and r0, r0, r2 157 beq reset_chk 158 bx lr 159 160 .global putchar 161 putchar: 162 uart0_write: 163 push {r4, r5, r6, r7, lr} 164 mov r4, #0xFF 165 and r4, r4, r0 166 ldr r5, uart0_base 167 mov r6, #32 // TXFF 168 uart0_txff: 169 ldr r7, [r5, #0x18] // UART0_UARTFR 170 and r7, r7, r6 171 bne uart0_txff 172 str r4, [r5, #0] // UART0_UARTDR 173 pop {r4, r5, r6, r7, pc} 174 175 .global getchar 176 getchar: 177 uart0_read: 178 push {r4, r5, r6, lr} 179 ldr r4, uart0_base 180 mov r5, #16 181 uart0_rxfe: 182 ldr r6, [r4, #0x18] // UART0_UARTFR 183 and r6, r6, r5 184 bne uart0_rxfe 185 ldr r0, [r4, #0] // UART0_UARTDR 186 mov r4, #0xFF 187 and r0, r0, r4 188 pop {r4, r5, r6, pc} 189 190 .global print 191 // void print(char *); 192 print: 193 push {r4, r5, lr} 194 mov r4, r0 195 mov r5, #0xFF 196 print_loop: 197 ldrb r1, [r4, #0] 198 and r1, r1, r5 199 beq print_end 200 mov r0, r1 201 bl uart0_write 202 add r4, r4, #1 203 b print_loop 204 print_end: 205 pop {r4, r5, pc} 206 207 .global printh 208 // void printh(uint32_t); 209 // print in hex 210 printh: 211 push {r4, r5, r6, lr} 212 mov r4, r0 213 mov r5, #0xF 214 mov r6, #28 215 printh_loop: 216 mov r0, r4 217 lsr r0, r0, r6 218 and r0, r0, r5 219 cmp r0, #10 220 blt printh_low 221 add r0, #'A' - 10 222 b printh_high 223 printh_low: 224 add r0, #'0' 225 printh_high: 226 bl putchar 227 sub r6, r6, #4 228 bge printh_loop 229 pop {r4, r5, r6, pc} 230 231 232 .global ldr 233 // uint32_t ldr(uint32_t addr) 234 // load content at addr 235 ldr: 236 ldr r0, [r0, #0] 237 bx lr 238 239 240 241 led_pr: 242 // print register with 2 leds 243 push {r0, r1, r2, r4, lr} 244 mov r4, r0 245 mov r1, #32 246 led_pr_loop: 247 mov r2, #1 248 and r2, r2, r4 249 beq led_pr_0 250 bl led_p1 251 b led_pr_1 252 led_pr_0: 253 bl led_p0 254 led_pr_1: 255 lsr r4, r4, #1 256 sub r1, #1 257 bne led_pr_loop 258 pop {r0, r1, r2, r4, pc} 259 260 led_p0: 261 // blink led on gpio22 262 push {r0, lr} 263 mov r0, #1 264 lsl r0, r0, #22 265 bl led_blink 266 pop {r0, pc} 267 268 led_p1: 269 // blink led on gpio24 270 push {r0, lr} 271 mov r0, #1 272 lsl r0, r0, #24 273 bl led_blink 274 pop {r0, pc} 275 276 .global led_p2 277 led_p2: 278 // blink led on gpio22 and gpio24 279 push {r0, lr} 280 mov r0, #5 281 lsl r0, r0, #22 282 bl led_blink 283 pop {r0, pc} 284 285 led_blink: 286 push {r0, r4, r5, lr} 287 ldr r4, sio_base 288 mov r5, r0 289 str r5, [r4, #0x10] // SIO_GPIO_OUT_SET 290 bl delay 291 str r5, [r4, #0x18] // SIO_GPIO_OUT_CLR 292 bl delay 293 pop {r0, r4, r5, pc} 294 295 .global delay 296 delay: 297 push {r0} 298 mov r0, #1 299 lsl r0, r0, #22 300 del_loop: 301 sub r0, r0, #1 302 bne del_loop 303 pop {r0} 304 bx lr 305 306 // data 307 308 .align 2 309 atomic_set: 310 .word 0x00002000 311 atomic_clr: 312 .word 0x00003000 313 xip_ssi_base: 314 .word 0x18000000 315 clocks_base: 316 .word 0x40008000 317 resets_base: 318 .word 0x4000c000 319 reset_done: 320 .word 0x4000c008 321 io_bank0_base: 322 .word 0x40014000 323 xosc_base: 324 .word 0x40024000 325 pll_sys_base: 326 .word 0x40028000 327 uart0_base: 328 .word 0x40034000 329 rosc_base: 330 .word 0x40060000 331 sio_base: 332 .word 0xd0000000