boot2.s (1155B)
1 .cpu cortex-m0plus 2 .thumb 3 4 .section .boot2 5 .global setup_xip 6 .thumb_func 7 setup_xip: 8 push {r4, lr} 9 10 // setup QSPI pad 11 ldr r4, pads_qspi_base 12 ldr r1, =(0 << 4 | 0 << 1 | 1) // 2mA, schmitt off, slew fast 13 str r1, [r4, #0x4] // PADS_QSPI: GPIO_QSPI_SCLK 14 15 ldr r4, rom_base 16 17 ldrh r0, [r4, #0x14] // rom_func_table 18 ldr r1, =('C' | 'X' << 8) // _flash_enter_cmd_xip() 19 ldrh r2, [r4, #0x18] // rom_table_lookup 20 blx r2 21 blx r0 22 23 // this code should be rewritten using dma. 24 ldr r2, boot2_end 25 ldr r3, sram_base 26 ldr r0, etext 27 sub r0, r0, r3 28 add r0, #3 29 lsr r0, #2 30 sram_cpy: 31 ldr r1, [r2, #0] 32 str r1, [r3, #0] 33 add r2, r2, #0x4 34 add r3, r3, #0x4 35 sub r0, r0, #0x1 36 bne sram_cpy 37 38 // exit from boot2 39 pop {r4} 40 pop {r0} 41 cmp r0, #0 42 beq initial_boot 43 bx r0 44 initial_boot: 45 ldr r0, sram_base 46 ldr r1, m0plus_vtor 47 str r0, [r1, #0] // M0PLUS: VTOR 48 ldr r1, [r0, #4] // entry point 49 ldr r0, [r0, #0] // stack pointer 50 mov sp, r0 51 bx r1 52 53 .align 2 54 rom_base: 55 .word 0x00000000 56 boot2_end: 57 .word 0x10000000 + 0x100 58 sram_base: 59 .word 0x20000000 60 pads_qspi_base: 61 .word 0x40020000 62 m0plus_vtor: 63 .word 0xe0000000 + 0xed08 64 etext: 65 .word _etext 66 literals: 67 .ltorg 68